Xilinx ZCU111 User Manual page 51

SI5382A SFP28 Clock Recovery
[Figure 2-1, callout 8]
The ZCU111 board includes a Silicon Labs SI5382A jitter attenuator U48. The RFSoC U1 PL
user logic can implement a clock recovery circuit and output this series capacitor coupled
clock from a differential pair on I/O bank 64 (SFP_REC_CLOCK_P U1 pin AW14 and
SFP_REC_CLOCK_N U1 pin AW13) for jitter attenuation. The jitter attenuated clock
(SFP_SI5382_OUT_P (U48 pin 21), SFP_SI5382_OUT_N (U48 pin 20)) is then routed as a series
capacitor coupled reference clock to GTY bank 128 inputs MGTREFCLK1P (U1 pin Y31) and
MGTREFCLK1N (U1 pin Y32).
The primary purpose of this clock is to support common packet radio interface/open base
station architecture initiative (CPRI/OBSAI) applications that perform clock recovery from a
user-supplied SFP28 module, and use the jitter attenuated recovered clock to drive the
reference clock inputs of a GTY transceiver. The jitter attenuated clock circuit is shown in
Figure 3-17.
ZCU111 Board User Guide
UG1271 (v1.1) August 6, 2018
Chapter 3: Board Component Descriptions
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