Xilinx ZCU111 User Manual page 55

Table 3-18 and
To provide external sources from the RFMC connector, the default capacitors must be
IMPORTANT:
carefully moved to optional capacitor locations.
Table 3-18: RFMC External Clocking Modifications
LMX2594 Device
Output Net Name
and Channel
U102 Channel A RF1_CLKO_A_P/N
U102 Channel B RF1_CLKO_B_P/N
U103 Channel A RF2_CLKO_A_P/N
U103 Channel B RF2_CLKO_B_P/N
U104 Channel A RF3_CLKO_A_P/N
U104 Channel B RF3_CLKO_B_P/N
By default, the LMK04208 provides a clock to the DAC bank 228 SYSREF clock input pins.
To provide an external SYSREF clock with the onboard optional SMAs, the default
IMPORTANT:
capacitors must be carefully moved to optional capacitor locations.
Table 3-19: SYSREF External Clocking Modifications
LMK04208 Device
Output Net Name
and Channel
U90 OUT1 P CLK_4208_OUT1_P
U90 OUT1 N CLK_4208_OUT1_N
Before making ZCU111 RF clock capacitor modifications, refer to the PC board layout and
identify the metal RF cage associated with the capacitors of interest:
• C632/C640, C646/C718: RFCAGE2
• C683/C690, C692/C699: REFCAGE3
• C666/C673, C675/C682: RFCAGE4
• C742 and C743: RFCAGE1
The appropriate cage lid must be removed to make the capacitor modifications, and
replaced upon completion.
To implement the external clock source capability, remove (desolder) the default capacitors
and solder them onto the pads at the optional external source capacitors locations shown in
the above tables (e.g., for
remove C640 and solder it at C949, and so on). Due to via-in-pad component footprints,
Xilinx recommends the rework be implemented by an expert rework technician.
ZCU111 Board User Guide
UG1271 (v1.1) August 6, 2018
Table 3-19 provides guidance on external clocking modifications.
FPGA Net Name
RF1_CLKO_A_C_P/N
RF1_CLKO_B_C_P/N
RF2_CLKO_A_C_P/N
RF2_CLKO_B_C_P/N
RF3_CLKO_A_C_P/N
RF3_CLKO_B_C_P/N
FPGA Net Name
SYSREF_RFSOC_C_P
SYSREF_RFSOC_C_N
Table 3-18, U102 Channel A, remove C632 and solder it at C948,
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Chapter 3: Board Component Descriptions
RFMC Optional
FPGA
External Clock
Bank
Net Name
224 ADCLK_IN0_P/N
225 ADCLK_IN1_P/N
227 ADCLK_IN2_P/N
226 ADCLK_IN3_P/N
228 DACLK_IN0_P/N
229 DACLK_IN1_P/N
FPGA ZCU111
Bank SYSREF SMA
228 J7
228 J10
Default Optional External
Capacitors Source Capacitors
C632 / C640 C948 / C949
C646 / C718 C1018 / C1019
C683 / C690 C951 / C950
C692 / C699 C1020 / C1021
C666 / C673 C1024 / C1025
C675 / C682 C1022 / C1023
Optional
Default External
Capacitors Source
Capacitors
C742 C1031
C743 C1034
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