Xm500 Adc/Dac Data And Clock Sma - Xilinx ZCU111 User Manual

XM500 ADC/DAC Data and Clock SMA

This section provides details on the XM500 ADC/DAC data and clock SMA, and I/O 2x10
header connectors to the ZCU111 board U1 RFSoC ZCU28DR channel mapping.
provides the XM500 ADC/DAC data and clock mapping.
Table D-2: XM500 ADC/DAC Data and Clock Mapping
SMA Ref. Des.
J26(P)/J27(N)
J20(P)/J21(N)
J22(P)/J23(N)
J24(P)/J25(N)
J33(P)/J32(N)
J34(P)/J35(N)
J37(P)/J36(N)
J39(P)/J40(N)
J30(P)/J31(N)
J889(P)/J890(N)
J891(P)/J892(N)
J893(P)/J894(N)
J28(P)/J29(N)
J896(P)/J895(N)
J898(P)/J897(N)
J900(P)/J899(N)
J9 2x10 header
J10 2x10 header
ZCU111 Board User Guide
UG1271 (v1.1) August 6, 2018
J7
J8
J5
J6
J4
J3
J2
J1
www.xilinx.com
ADC/DAC Data or Clock
DAC228_T0_Ch0
DAC228_T0_Ch1
DAC228_T0_Ch2
DAC228_T0_Ch3
DAC229_T1_Ch0
DAC229_T1_Ch1
DAC229_T1_Ch2
DAC229_T1_Ch3
ADC224_T0_Ch0
ADC224_T0_Ch1
ADC225_T1_Ch0
ADC225_T1_Ch1
ADC226_T2_Ch0
ADC226_T2_Ch1
ADC227_T3_Ch0
ADC227_T3_Ch1
ADC224_T0_CLKIN
ADC225_T1_CLKIN
ADC226_T2_CLKIN
ADC227_T3_CLKIN
DAC228_T0_CLKIN
DAC229_T1_CLKIN
DAC230_T2_CLKIN
DAC231_T3_CLKIN
See Figure D-5
See Figure D-5
Appendix D: HW-FMC-XM500
Table D-2
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