Xilinx ZCU111 User Manual page 68

Table 3-24: GPIO Connections to XCZU28DR (Cont'd)
XCZU28DR (U1) Pin
AF17
AH15
AH16
AH17
AG17
AJ15
AJ16
AW3
AW6
AW5
AW4
E8
AF15
Notes:
1. Level-shifted net names at ZU28DR U1 have _LS appended.
ZCU111 Board User Guide
UG1271 (v1.1) August 6, 2018
Net Name
GPIO_DIP_SW1
GPIO_DIP_SW2
GPIO_DIP_SW3
GPIO_DIP_SW4
GPIO_DIP_SW5
GPIO_DIP_SW6
GPIO_DIP_SW7
Directional Pushbuttons (Active High)
GPIO_SW_N
GPIO_SW_W
GPIO_SW_C
GPIO_SW_E
GPIO_SW_S
CPU Reset Pushbutton (Active High)
CPU_RESET
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Chapter 3: Board Component Descriptions
I/O Standard Device
LVCMOS18 SW14.7
LVCMOS18 SW14.6
LVCMOS18 SW14.5
LVCMOS18 SW14.4
LVCMOS18 SW14.3
LVCMOS18 SW14.2
LVCMOS18 SW14.1
LVCMOS18 SW9.3
LVCMOS18 SW10.3
LVCMOS18 SW11.3
LVCMOS18 SW12.3
LVCMOS18 SW13.3
LVCMOS18 SW15.3
68
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