I2C1 (Mio 16-17) - Xilinx ZCU111 User Manual

Table 3-5: I2C0 Multiplexer PCA9544A U23 Addr. 0x75 Connections
PCA9544A U23
Schematic Net Name
Pin
Pin No.
Name
SDA 19 I2C0_SDA
SCL 18 I2C0_SCL
Port Mux'd I2C Bus
0 INA226_PMBUS_SDA/SCL
2 IRPS5401_SDA/SCL
3 SYSMON_SDA/SCL
Notes:
1. SYSMON SDA/SCL are level-shifted via U99.

I2C1 (MIO 16-17)

[Figure 2-1, callout 14]
The I2C bus I2C1 connects the RFSoC U1 PS bank 500, PL bank 64, and system controller
U42 to two I2C switches (TCA9548A U26 and U27). These I2C1 connections enable I2C
communications with other I2C capable target devices. TCA9548A U26 is pin-strapped to
respond to I2C address 0x74. TCA9548A U27 is pin-strapped to respond to I2C address
0x75. Figure 3-4
Table 3-6 and Table
ZCU111 Board User Guide
UG1271 (v1.1) August 6, 2018
Pin No.
4/5
19/18
D11/B12
shows a high-level view of the I2C1 bus connectivity represented in
3-7.
www.xilinx.com
Chapter 3: Board Component Descriptions
Connected To
Pin Name Reference Designator
Refer to connections shown in
PCA9544A U23 Addr. 0x75
SDA/SCL See P17 in
DATA/CLK U53,U55,U57
Bank 68 U1
Device
Figure 3-3.
Table 3-4 INA226
IRPS5401
(1)
XCZU28DR
31
Send Feedback