Xilinx ZCU111 User Manual page 54

Figure 3-18 shows the bank view of the ZCU111 RF clocking structure.
X-Ref Target - Figure 3-18
FPGA SMA: AMS_FPGA_REF_CLK
Bank
64
TCXO
SMA External REF
/2
Clock
Buffer
/2
LMK00304
/2
Figure 3-18: RF Clocking Structure for ADC and DAC Banks
ZCU111 Board User Guide
UG1271 (v1.1) August 6, 2018
VCXO
122.88 MHz
Loop
Filter
CPout1 OSCin
CLKin0
PLL1
(incl. VCO)
CLKin1
LMK04208
Sync
Buffer
LMK00804
/1
RF outA Capacitor Option
RF1_CLK0_A
LMX2594
RF1 PLL
RF1_CLK0_B
Capacitor Option
RF outB
RF outA Capacitor Option
RF2_CLK0_A
LMX2594
RF2 PLL
RF2_CLK0_B
Capacitor Option
RF outB
RF outA
Capacitor Option
RF3_CLK0_A
LMX2594
RF3 PLL
RF outB
RF3_CLK0_B
Capacitor Option
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Chapter 3: Board Component Descriptions
CLKout0
CLKout1
PLL2
Dividers
CLKout2
CLKout5
CLKout3
CLKout4
REFIN_2594
SYNC
ADCLK_IN0-3
/8 (4 pairs)
ADC Bank 224
2 ADC, 1 CLKIN
ADC Bank 225
2 ADC, 1 CLKIN
ADC Bank 226
/2
2 ADC, 1 CLKIN
ADC Bank 227
/2
2 ADC, 1 CLKIN
/4 (2 pairs) DACLK_IN0-1
DAC Bank 228
4 DAC, 1 CLKIN
DAC Bank 229
SYSREF_RFSoC
4 DAC, 1 CLKIN
/2
Optional DAC:
SYSREF_RFSOC
Capacitor
Option
MPSoC PL: SYSREF_FPGA
/2
MPSoC DAC: SYSREF_RFSOC
/2
MPSoC PL: FPGA_REFCLK_OUT
/2
SMA: ~10 MHz REF Out
/1
/2
/2
ADC0
ADC1
ADC
Connector
Samtec
LPAF
ADC2 8x40
ADC3
DAC0
DAC
Connector
Samtec
LPAF
8x40
DAC1
X21144-062818
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