Xilinx ZCU111 User Manual page 74

X-Ref Target - Figure 3-30
Bank 505 DP (DisplayPort) lanes 0 and 1 TX support the 2-channel source only PS-side
DisplayPort circuitry described in
Bank 505 USB0 lane 2 supports the USB3.0 interface described in
USB 2.0 ULPI PHY, page
Bank 505 SATA1 lane 3 supports the M.2 SATA connector U170 as shown in
Bank 505 reference clocks are connected to the U46 SI5341B clock generator as detailed in
SI5341B 10 Independent Output Any-Frequency Clock Generator, page
Bank 505 connections are referenced in
ZCU111 Board User Guide
UG1271 (v1.1) August 6, 2018
Figure 3-30: PS-GTR Lane Assignments
DPAUX (MIO 27-30), page
39.
Appendix B, Xilinx Design
www.xilinx.com
Chapter 3: Board Component Descriptions
X20565-062118
35.
USB 3.0 Transceiver and
47.
Constraints.
Send Feedback
Figure 3-31.
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