Adc/Dac Bank Data And Clock Channel Mapping - Xilinx ZCU111 User Manual

ADC/DAC Bank Data and Clock Channel Mapping

This section provides details on the ZCU111 board U1 RFSoC ZCU28DR ADC/DAC bank data
and clock channel mapping.
ZC28DR bank RF channel mapping and RF bank connectivity.
X-Ref Target - Figure D-3
FPGA
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Figure D-3: RFSoC ZCU28DR ADC/DAC Bank Channel Mapping
ZCU111 Board User Guide
UG1271 (v1.1) August 6, 2018
Figure D-3
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and Figure D-4 show the ZCU111 board U1 RFSoC
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Appendix D: HW-FMC-XM500
AMC
ADC_00
ADC_01
ADC_02
ADC_03
ADC_04
ADC_05
ADC_06
ADC_07
DAC_00
DAC_01
DAC_02
DAC_03
DAC_04
DAC_05
DAC_06
DAC_07
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