Xilinx ZCU111 User Manual page 46

Table 3-17 lists the connections for each clock.
Table 3-17: Clock Connections to XCZU28DR U1
Clock Source Ref.
Des. and Pin
U46.59
U46.45
U46.44
U46.42
U46.41
U46.35
U46.34
U46.31
U46.30
U46.24
U46.23
U47.4
U47.5
U49.4
U49.5
J14
J15
U48.1
U48.2
U48.21
U48.20
U48.63
U48.64
Notes:
1. U1 XCZU28DR bank 503 supports LVCMOS18 level inputs.
2. Series capacitor coupled, U1 MGT (I/O standards do not apply).
3. Series capacitor coupled.
ZCU111 Board User Guide
UG1271 (v1.1) August 6, 2018
Net Name
U46 SI5341B Clock Generator
PS_REF_CLK (series R310)
CLK_125_P
CLK_125_N
CLK_100_P
CLK_100_N
GTR_REF_CLK_SATA_P
GTR_REF_CLK_SATA_N
GTR_REF_CLK_USB3_P
GTR_REF_CLK_USB3_N
GTR_REF_CLK_DP_P
GTR_REF_CLK_DP_N
U47 SI570 I2C Prog. Oscillator (300 MHz default)
USER_SI570_P
USER_SI570_N
U49 SI570 I2C Prog. Oscillator (156.250 MHz default)
USER_MGT_SI570_P
USER_MGT_SI570_N
J14 (P)/J15 (N) SMA Connectors
USER_SMA_MGT_CLOCK_P
USER_SMA_MGT_CLOCK_N
U48 SI5382A Clock Recovery
SFP_SI5382_IN1_P
SFP_SI5382_IN1_N
SFP_SI5382_OUT_P
SFP_SI5382_OUT_N
SFP_REC_CLOCK_P
SFP_REC_CLOCK_N
www.xilinx.com
Chapter 3: Board Component Descriptions
I/O Standard
(1)
LVDS
LVDS
LVDS
LVDS
(2)
(2)
(2)
(2)
(2)
(2)
LVDS
LVDS
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(3)
LVDS
(3)
LVDS
Send Feedback
XCZU28DR (U1)
Pin
AC30
AL17
AM17
AM15
AN15
AC34
AC35
AE34
AE35
AG34
AG35
J19
J18
V31
V32
T31
T32
AA33
AA34
Y31
Y32
AW14
AW13
46