Privilege Violations; Tracing - Motorola MC68306 User Manual

instructions using the opcodes of any of the illegal instructions. Three bit patterns always
force an illegal instruction trap on all M68000 family-compatible microprocessors. The
patterns are: $4AFA, $4AFB, and $4AFC. Two of the patterns, $4AFA and $4AFB, are
reserved for Motorola system products. The third pattern, $4AFC, is reserved for customer
use (as the take illegal instruction trap (ILLEGAL) instruction).
Word patterns with bits 15–12 equaling 1010 or 1111 are distinguished as unimplemented
instructions, and separate exception vectors are assigned to these patterns to permit
efficient emulation. These separate vectors allow the operating system to emulate
unimplemented instructions in software.
Exception processing for illegal instructions is similar to that for traps. After the instruction
is fetched and decoding is attempted, the processor determines that execution of an illegal
instruction is being attempted and starts exception processing. The exception stack frame
is then pushed on the supervisor stack, and the illegal instruction vector is fetched.

4.6.7 Privilege Violations

To provide system security, various instructions are privileged. An attempt to execute one
of the privileged instructions while in the user mode causes an exception. The privileged
instructions are as follows:
AND Immediate to SR
EOR Immediate to SR
MOVE to SR
MOVE from SR
MOVEC
MOVES
Exception processing for privilege violations is nearly identical to that for illegal
instructions. After the instruction is fetched and decoded and the processor determines
that a privilege violation is being attempted, the processor starts exception processing.
The status register is copied; the supervisor mode is entered; and tracing is turned off.
The vector number is generated to reference the privilege violation vector, and the current
program counter and the copy of the status register are saved on the supervisor stack.
The saved value of the program counter is the address of the first word of the instruction
causing the privilege violation. Finally, instruction execution commences at the address in
the privilege violation exception vector.

4.6.8 Tracing

To aid in program development, the EC000 core includes a facility to allow tracing
following each instruction. When tracing is enabled, an exception is forced after each
instruction is executed. Thus, a debugging program can monitor the execution of the
program under test.
The trace facility is controlled by the T-bit in the supervisor portion of the status register. If
the T-bit is cleared (off), tracing is disabled and instruction execution proceeds from
instruction to instruction as normal. If the T-bit is set (on) at the beginning of the execution
of an instruction, a trace exception is generated after the instruction is completed. If the
MOTOROLA
MOVE USP
OR Immediate to SR
RESET
RTE
STOP
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