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Logic function blocks
The input variable to INPUT is obtained delayed a settable time T at output ON when
the input variable changes from 0 to 1 in accordance with the time pulse diagram, figure
13. The output ON signal returns immediately when the input variable changes from 1
to 0.
INPUT
ON
0
1 1
2
3
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If more timers than available in the terminal are needed, it is possible to use pulse timers
with AND or OR logics. Figure 14 shows an application example of how to realize a
timer delayed on pick-up. Figure 15 shows the realization of a timer delayed on drop-
out. Note that the resolution of the set time must be 0.2 s, if the connected logic has a
cycle time of 200 ms.
INPUT
T
0.00-60.00s
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T=3s
4
5
6
7
8
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Pulse
OUT
NOUT
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1
0
1
0
9
10
AND
INPUT1
OUT
INPUT2
NOUT
INPUT3
INPUT4N
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39
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