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14.2 RESET FUNCTION
Power-on reset is applied when V
from low level to high level.
Power-on reset initializes the program counter, stack, system register and control registers, and executes
the program from address 0000H.
CE reset initializes the program counter, stack, system register and some control registers, and executes
the program from address 0000H.
The main differences between power-on reset and CE reset are the operation of the control registers that
are initialized and the power failure detection circuit described in Section 14.6.
Power-on reset and CE reset are controlled by reset signals IRES, RES, and RESET output from the reset
control circuit in Fig. 14-1.
Table 14-1 shows the IRES, RES, and RESET signal and power-on reset and CE reset relationship.
The reset control circuit also operates when the clock-stop instruction (STOP) described in Chapter 13 is
executed.
Sections 14.3 and 14.4 describe CE reset and power-on reset, respectively.
Section 14.5 describes the relationship between CE reset and power-on reset.
Table 14-1 Relationship between Internal Reset Signal and Each Reset
Internal reset signal
At CE reset
IRES
RES
RESET
172
rises from a certain voltage, CE reset is applied when the CE pin rises
DD
Output signal
At power-
At clock-stop
on reset
Contents controlled by each reset signal
Forces the device into the halt state.
The halt state is released by the setting of the
timer carry FF.
Initializes some control registers.
Initializes the program counter, stack, system
register, and some control registers.
PD17062
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