NEC PD17062 Datasheet page 132

Mos integrated circuit 4-bit single-chip microcontroller containing pll frequency synthesizer and image display controller
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#
In
, specify the data memory bank containing the contents of the system register.
Because the bank becomes BANK0 when an interrupt is accepted, if the data is saved in BANK0, this
instruction is not necessary.
$
In
, save the contents of the window register in data memory M1.
Because the POKE instruction is used, the address of data memory M1 should be 40H or more. Because
the window register is used as a work area for subsequent data saving, its contents must be saved first.
%
In
, save the interrupt permission flags (IPNC, IPBMT0, and IPVSYN) set when interrupts are accepted.
In this example, all INT
pin, V
NC
the main routine in this save operation. The priority of the timer interrupt is higher than that of the INT
Therefore, if the timer interrupt is accepted while the INT
be returned with the INT
&
NC
In
, permit V
interrupt with a lower priority than the timer interrupt. Then, use the EI instruction to
SYNC
permit all interrupts.
#
Because processing in
with the highest priority is also inhibited during this processing.
(
)
In
and
, save and restore the contents of the system and control registers. At this time, interrupts with
high priorities can be enabled.
If the contents of the registers are saved when a V
of the system and control registers do not change when control is returned from V
*
+
In
and
, return the contents of the interrupt permission flag and window register.
At this time, all interrupts should be inhibited.
If a timer interrupt is issued when the instruction in
the contents of the window register in
of the window register cannot be restored.
132
pin, and timer interrupts must be permitted when control is returned to
SYNC
pin interrupt inhibited.
$
%
&
,
,
, and
must be executed with an interrupt inhibited, the V
SYNC
+
are not restored but are saved again in
pin interrupt is being processed, control should
NC
interrupt with a high priority is accepted, the contents
*
that permits an interrupt is executed in an EI state,
$
PD17062
pin.
NC
interrupt
SYNC
interrupt processing.
SYNC
. At this time, the contents

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