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13.5 CLOCK STOP FUNCTION
The clock stop function stops the operation of the 8 MHz crystal oscillator by executing the STOP s
instruction.
The clock stop function can reduce the current drain of the PD17062 by 10 A (maximum).
The operand s of the STOP s instruction is 0000B.
This instruction is effective only when the CE pin is at a low level. If executed when the CE pin is at a high,
the STOP s instruction is regarded as a no-operation instruction (NOP).
In other words, the STOP s instruction should be executed when the CE pin is at a low.
A CE reset is used to release the clock stop state.
Sections 13.5.1 to 13.5.3 describe the clock stop state, how to release the clock stop state, and cautions
to be taken in using the clock stop instruction.
13.5.1 Clock Stop State
In the clock stop state, all operations of the device, including CPU and peripheral hardware operations, are
stopped, because the crystal oscillator stops.
During the clock stop state, the power-failure detector does not operate even if the supply voltage V
lowered to about 2.2 V. This makes possible a low-voltage data memory backup.
13.5.2 Releasing the Clock Stop State
The clock stop state is released by raising the level of the CE pin from a low to a high (CE reset) or by lowering
the supply voltage V
of the device below 2.2 V, then increasing it to 4.5 V (power-on reset).
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Figs. 13-4 and 13-5 show how the clock stop state is released by a CE reset and power-on reset, respectively.
Releasing the clock stop state using a power-on reset causes the power-failure detector to start operating.
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