Table of Contents
Advertisement
16.5 PRESETTABLE SHIFT REGISTER (PSR)
The presettable shift register is an 8-bit register. It outputs the contents of the most significant bit of the
PSR to the serial data output pin (P0A
edge of the clock signal on the shift clock pin (P0A
of the serial data input pin (P0A
synchronously with the rising edge of the clock.
In the wait state, the shift clock is not supplied to PSR. In other words, the PSR does not shift data in the
wait state even if a clock (internal or external) is supplied to the shift clock pin (internally or externally) .
The operation of the PSR that is not in the wait state varies between two-wire bus mode and serial I/O mode.
Data is written to the PSR by the PUT instruction and read from the PSR by the GET instruction via the 8
low-order bits (data memory address: 0EH, 0FH) of DBF in data memory.
(1) PSR operation in two-wire bus mode
If two-wire bus mode is specified, the shift clock is supplied to the PSR only while the clock counter is
set to 1 to 8. For example, to receive 9-bit data (8-bit data + 1-bit acknowledgement) in two-wire bus mode,
the first 8 bits of data are read into the PSR. Then, the 9th bit is read into the SBACK flag of the wait register.
When the contents of the PSR are transmitted in two-wire bus mode, the contents of the PSR are output
to the serial data pin while the clock counter is set to 1 to 8, and the contents of the SBACK flag are output
while the clock counter is set to 9 (more precisely, between the fall of the 8th bit clock to the rise of the
9th bit clock).
The PSR operates as described above not only when using the hardware of the serial interface of the
PD17062 (also when using internal or external clock) but also when the clock is generated by the software
with the port (P0A
) also used as the shift clock pin set as an output port.
0
During transmission, data output to the SDA pin is again read into the PSR synchronously with the rise
of the next shift clock. Therefore, in transmission also, once the shift clock has been output 8 times, data
on the pin being transmitted is stored in the PSR. If no data conflict occurs during transmission, the data
stored into the PSR will be exactly the same as that before the transmission. Hence, the data before
transmission and PSR data after transmission can be compared to determine whether the data was
transmitted normally.
The above explanation applies to a PSR that is not in the wait state, the PSR does not perform any shift
operations.
(2) PSR operation in serial I/O mode
When serial I/O mode is specified, the shift clock supply to the PSR is not related to the contents of the
clock counter. The PSR performs a shift operation according to the clock in the shift clock pin unless it
is currently in the wait state.
The PSR does not perform any shift operations in the wait state. Hence, when the PSR is used merely
for data storage, not as a serial interface, the PSR must be set to the wait state.
In serial I/O mode, data must be written to the PSR or read from the PSR when the shift clock is at the
high level or in the wait state. If data is written or read at any other time, the PSR will not operate normally.
Normally, when the internal clock is used, wait should occur with the rise of the 8th bit clock, and the PSR
should be manipulated during this wait state. When the external clock is used, the PSR should be
manipulated while the high level of the shift clock is checked by the transmission side.
214
/SDA pin for CH0, P0A
0
/SCL pin for CH0, P0A
1
/SDA pin for CH0, P0B
/SI pin for CH1) into the least significant bit of the PSR
0
0
/SO pin for CH1) synchronously with the falling
3
/SCK pin for CH1) and reads the data
2
PD17062
Advertisement
Table of Contents
