Pll Frequency Synthesizer; Pll Frequency Synthesizer Configuration - NEC PD17062 Datasheet

18. PLL FREQUENCY SYNTHESIZER

18.1 PLL FREQUENCY SYNTHESIZER CONFIGURATION

Fig. 18-1 is a block diagram of the PLL frequency synthesizer.
As shown in Fig. 18-1, the PLL frequency synthesizer consists of a programmable divider (PD), phase
comparator ( -DET), reference frequency generator (RFG), and charge pump. Strictly speaking, a PLL
frequency synthesizer is configured by connecting these blocks with an external lowpass filter (LPF) and
voltage-controlled oscillator (VCO).
See Sections 18.3 to 18.5 for details of these blocks.
Register
VCO
Note
Prescaler PB595
Note External circuit
Fig. 18-1 PLL Frequency Synthesizer Block Diagram
Data buffer
Programmable
divider (PD)
Reference frequency
generator (RFG)
PSC
Voltage-controlled
oscillator (VCO)
Unlock detection
block
Phase
comparator
Charge pump
( -DET)
Note
Lowpass filter
(LPF)
PD17062
EO
Note
219