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Table 9-1 Peripheral Hardware Control Functions of Control Registers (2/5)
Control register
Register
Ad-
Read/
dress
write
Interrupt edge
1FH
R/W
select register
Interrupt
permission
2FH
R/W
register
Interrupt
request
3FH
R
register
CE pin level
07H
R
judge register
PLL reference
clock select
13H
R/W
register
PLL unlock
22H
R
flip-flop judge
register
PLL unlock
flip-flop
32H
R/W
sensibility
select register
Remark *: Retains the previous state.
Peripheral hardware control function
b3
b2
Symbol
Function outline
b1
b0
0
Fixed at 0
Sets the interrupt issue edge (V
IEGVSYN
0
Fixed at 0
IEGNC
Sets the interrupt issue edge (INT
IPSIO0
- Serial interface 0
IPVSYN
- V
signal
SYNC
- Basic timer 0
IPBTM0
- INT
pin
NC
IPNC
IRQSIO0
- Serial interface 0
IRQVSYN
- V
signal
SYNC
- Basic timer 0
IRQBTM0
- INT
pin
NC
IRQNC
0
0
Fixed at 0
0
Detects the CE pin state
CE
PLLRFCK3
PLLRFCK2
Fixed at 1
PLLRFCK1
PLLRFCK0
0
Fixed at 0
0
0
Detects the unlock flip-flop state
PLLUL
0
Fixed at 0
0
PLULSEN1
Sets the set delay time for
the unlock flip-flop
PLULSEN0
Set value
0
)
Rising edge
Falling edge
SYNC
Rising edge
Falling edge
)
NC
Sets
the in-
Interrupt
Interrupt
terrupt
disabled
enabled
permis-
sion of:
Sets
No interrupt
the in-
Interrupt
request/
terrupt
request made
processing
request
in progress
of:
Low level
High Level
2: 6.25 kHz
3: 12.5 kHz
6: 25 kHz
F: Operation stopped (disabled state)
0, 1, 4, 5, 7-E: Setting disabled
Locked state
Unlocked state
0
0
1
1.25
3.5
0.25
to
to
to
1.5 s
3.75 s 0.5 s
0
1
0
PD17062
At reset
P
S
C
o
T
E
w
O
e
P
r
O
1
n
0 0
0
0 1
1
0 0
0
0 –
–
F F
*
0 *
*
1
0 0
*
Disabled
state
1
71
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