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(2) When two or more interrupts (e.g., rising edge at the INT
(a) Hardware priorities
MOV
Instruction
WR, #0101B
INTE
INT
pin
NC
IRQNC flag
V
pin
SYNC
IRQVSYN flag
IPNC flag
IPVSYN flag
(b) Software priorities
MOV
Instruction
WR, #0100B
INTE
INT
pin
NC
IRQNC flag
V
pin
SYNC
IRQNC flag
IPNC flag
IPVSYN flag
Fig. 11-3 Interrupt Acceptance Timing Chart
Interrupt
POKE
EI
INTPM, WR
cycle
INT
pin interrupt holding period
NC
V
INT
pin interrupt acceptance
NC
POKE
Interrupt
EI
INTPM, WR
cycle
V
pin interrupt holding period
SYNC
V
pin interrupt acceptance
SYNC
pin and falling edge at the V
NC
EI
INT
pin interrupt processing
NC
pin interrupt holding period
SYNC
V
pin interrupt acceptance
SYNC
MOV
POKE
EI
WR, #0101B
INTPM, WR
INT
pin interrupt holding period
NC
V
pin interrupt processing
SYNC
PD17062
pin) are used
SYNC
Interrupt
cycle
V
pin
SYNC
interrupt processing
Interrupt
cycle
INT
pin interrupt
NC
processing
INT
pin interrupt acceptance
NC
115
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