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Table 9-1 Peripheral Hardware Control Functions of Control Registers (4/5)
Control register
Register
Ad-
Read/
dress
write
Serial I/O0
status judge
28H
R
register
Serial I/O0
interrupt
38H
R/W
mode
register
Serial I/O0
clock select
39H
R/W
register
H
counter
SYNC
11H
R/W
gate control
register
H
counter
SYNC
gate judge
12H
R
register
Remark *: Retains the previous state. **: Indefinite
Peripheral hardware control function
b3
b2
Symbol
Function outline
b1
b0
SIO0SF8
Detects the contents of clock
counter
SIO0SF9
Detects the number of clocks
SBSTT
(I
2
C bus method)
Detects the start condition
SBBSY
(I
C bus method)
2
0
Fixed at 0
0
SIO0IMD1
Sets the interrupt condition
of serial interface 0
SIO0IMD0
0
Fixed at 0
0
SIO0CK1
Sets the internal clock of
serial interface 0
SIO0CK0
0
Fixed at 0
0
HSCGT1
Controls the H
SYNC
counter gate
HSCGT0
Detects open/close of the H
HSCGOSTT
0
0
Fixed at 0
0
Set value
0
Resets when
Resets when
the contents of
the contents of
the clock counter
the clock counter
become 0 or 1
become 8
Resets when
Resets when
the contents of
the contents of
the clock counter
the clock counter
become 0 or 1
become 9
Sets up the start condition - 9th clock
Sets up the start condition -
stop condition
0
0
1
7th clock
7th
8th
after occur-
rence of start
clock
clock
condition
0
1
0
0
0
1
100
200
500
kHz
kHz
kHz
0
1
0
0
0
1
1.69 ms
Gate
Gate
gate
close
open
open
0
1
0
counter
Gate close
SYNC
PD17062
At reset
S
C
P
o
T
E
w
O
e
P
r
O
1
n
0
0
0
1
** *
*
Stop
con-
dition
1
1
** *
*
1
MHz
1
1
0
0
0
Not to
be set
1
Gate open
0
–
–
73
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