NEC PD17062 Datasheet page 44

Mos integrated circuit 4-bit single-chip microcontroller containing pll frequency synthesizer and image display controller
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Example 2.
When BANK0 is selected and MPE = 0 is specified
MOV 04H, #8
AND RPL, #0001B
MOV @04H, 52H
Executing the above instruction transfers the contents of data memory address 52H to address 58H. The
MOV @r, m instruction is called an indirect transfer of the general-purpose register contents. In this
instruction, the contents of the general-purpose register address specified in r (8 in the above example) consist
of the column address of data memory, and the row address specified in m (5 in the above example) is the
row address of data memory. That is, the data memory address is 58H (see Fig. 6-3).
See Section 8.5 for an explanation of the indirect transfer of the general-purpose register contents.
0
0
1
2
3
4
5
6
7
Example 3.
AND RPL,
MOV BANK, #0010B ; BANK2
LD
01H,
LD
02H,
LD
03H,
LD
04H,
OR
RPL,
LD
05H,
LD
06H,
LD
07H,
LD
08H,
44
; 04H
8
; RP
0000000B; The general-purpose register is allocated in row
; address 0H in BANK0.
Fig. 6-3 Execution of Instructions in Example 2
Column address
1
2
3
4
5
6
7
8
General-purpose register
MOV
@ 04H, 56H
M
System register
#0000B ; RP
0000000B; The general-purpose register is allocated in row
; address 0H of BANK0.
31H
32H
33H
34H
#1000B ; RP
0000100B; The general-purpose register is allocated in row
; address 4H of BANK0.
45H
46H
47H
48H
8
9
A
B
C
D
E
BANK0
RP
PD17062
F

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