NEC PD17062 Datasheet page 130

11.9.3 Interrupt Level Restriction by Address Stack Register
The return address at control return from interrupt processing is automatically saved in the address stack
register.
The address stack register can use the six levels from ASR0 to ASR5 as described in Chapter 4. Because
the interrupt sources are the INT
unlimited when the address stack register is used only for interrupts.
However, because the address stack register is also used to save the return address at subroutine calling,
multiple interrupt levels are limited according to the levels of the address stack register used for subroutine
calling.
For example, if four levels are used for subroutine calling, only two levels of the multiple interrupts shown
in Fig. 11-10 can be used.
Level 0
Address stack
register
ASR0
ASR1 Undefined
ASR2 Undefined
ASR3 Undefined
ASR4 Undefined
ASR5 Undefined
Stack
ASR6 Undefined
pointer
SP ASR7
Main routine
MAIN:
SUB1:
130
pin, timer, V
NC SYNC
Fig. 11-10 Address Stack Register Operation
Level 1 Level 2 Level 3
Undefined Undefined Undefined
Undefined Undefined Undefined
Undefined Undefined Undefined
Undefined Undefined SUB2
Undefined SUB1 SUB1
MAIN MAIN MAIN
Subroutine Subroutine Subroutine
1 2
SUB2: SUB3:
pin, and serial interface, the multiple interrupt level is
Level 4 Level 5
Undefined Undefined
Undefined AAA
SUB3 SUB3
SUB2 SUB2
SUB1 SUB1
MAIN MAIN
Interrupt Subroutine
3 A 4
AAA: SUB4:
Because the contents of the address stack register
(ASR0) are always undefined when the stack pointer
is 0, the return addressof the RET instruction also
becomes undefined.
PD17062
Level 6 Level 7 Level 8
SUB4 SUB4
AAA AAA
SUB3 SUB3
SUB2 SUB2
SUB1 SUB1
MAIN MAIN
Interrupt Subroutine
B 5
BBB:
RET
MAIN
SUB4
AAA
SUB3
SUB2
SUB1