Table of Contents
Advertisement
9.1 IDCDMAEN (00H, b
)
1
This flag must be set to enable the operation of IDC.
When the IDCDMAEN flag is set, the mode changes to DMA mode and IDC is enabled. In DMA mode, the
instruction cycle is seen as 12 s. For details, see Chapter 20.
00H
b
b
b
3
2
0
0
IDCDMAEN
9.2 SP (01H)
SP is a pointer that addresses the stack register.
01H
b
b
b
3
2
0
(SPb
)
(SPb
2
b
1
0
0
0
DMA prohibited mode (instruction cycle = 2 s)
1
DMA mode (instruction cycle = 12 s)
b
1
0
)
(SPb
)
1
0
SP (stack pointer)
0
0
0
Level 6
0
0
1
Level 5
0
1
0
Level 4
0
1
1
Level 3
1
0
0
Level 2
1
0
1
Level 1
1
1
0
At reset
1
1
1
Not to be set
PD17062
75
Advertisement
Table of Contents
