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BLOCK DIAGRAM
VCO
PLL
PSC
EO
H
SYNC
V
SYNC
IDC
RED
GREEN
BLUE
BLANK
P0A
/SDA
0
P0A
/SCL
1
Serial
P0A
/SCK
2
I/O
P0A
/SO
3
P0B
/SI
0
P0A
P0B
1
P0B
P0B
/TMIN
2
P0B
/HSCNT
3
Hsync Counter
Timer Controller
P0D
/ADC
0
2
P0D
/ADC
1
3
P0D
P0D
/ADC
2
4
P0D
/ADC
3
5
P1C
/ADC
3
1
P1C
P1C
2
P1C
1
A/D
ADC
0
RF
RAM
336
4 bits
(Including VRAM)
SYSREG
ALU
ROM
3968
16 bits
(Including CROM)
Instruction
Decoder
Program Counter
Peripheral
Stack 6
12 bits
PD17062
PWM
PWM
PWM
PWM
P1A
P1A
P1A
P1A
P1A
P1B
P1B
P1B
P1B
P1B
P0C
P0C
P0C
P0C
P0C
Interrupt
INT
Controller
CPU
X
IN
OSC
X
OUT
V
DD
Reset
CE
GND
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
NC
5
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