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11.3 INTERRUPT ACCEPTANCE
11.3.1 Interrupt Acceptance and Priority
An interrupt is accepted as follows:
(1) When the interrupt conditions are satisfied (e.g., a rising edge is input to the INT
peripheral hardware outputs the interrupt request signal to the interrupt request blocks.
(2) When an interrupt request block accepts an interrupt request signal from the peripheral hardware, it sets
the corresponding IRQ
(3) If an interrupt permission flag corresponding to an IRQ
each interrupt request flag is set, each interrupt request block outputs a 1.
(4) A signal output from each interrupt request block is input to the interrupt enable flip-flop via an OR circuit.
This interrupt enable flip-flop is set to 1 by the EI instruction and reset by the DI instruction.
If a 1 is output from each interrupt request block while the interrupt enable flip-flop is set, a 1 is output
from the interrupt enable flip-flop and the interrupt is accepted.
When the interrupt is accepted, the signal from the interrupt enable flip-flop is input to the interrupt request
block via an AND circuit as shown in Fig. 11-1.
The interrupt request flag is reset by the signal input to each interrupt request block, and the vector address
for each interrupt is output.
If a 1 is output from the interrupt request block at this time, the interrupt acceptance signal is not
transferred to the next level. If two or more interrupt requests are issued together, they are accepted in
the following sequence:
(DMA) > INT
pin > timer > V
NC
This sequence is called the hardware priority.
Fig. 11-2 shows the interrupt acceptance flowchart.
#
The processing in
of Fig. 11-2 is always executed in parallel. If two or more interrupt requests are
generated at the same time, the interrupt request flags are set at the same time.
On the other hand, the processing in
permission flags.
In other words, if an interrupt permission flag is not set, the interrupt from the interrupt source is not
accepted. An interrupt with a high hardware priority can be inhibited by resetting the corresponding interrupt
permission flag in the program.
This type of interrupt is called a maskable interrupt. For a maskable interrupt, an interrupt with a high
hardware priority can be inhibited by the program; therefore, it is also called the software priority.
flag to 1 (e.g., sets IRQNC for the INT
pin > serial interface
SYNC
$
is executed according to the priority given by the interrupt
NC
pin).
NC
(e.g., IPNC flag for the IRQNC flag) is set 1 when
PD17062
pin), each type of
111
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