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(1) PLL unlock FF judge register (PLLULJDG)
This register is a read-only register. It is reset when its content is read into a window register (WR) with
a PEEK instruction.
Because the unlock FF is set at intervals of the period (1/f
this register must be read into the window register at intervals larger than the period of the reference
frequency.
Fig. 18-7 Configuration and Functions of the PLL Unlock FF Judge Register (PLLULJDG)
Register
b
PLL unlock FF
0
judge register
(PLLULJDG)
Power-on
0
Clock stop
CE
* Undefined
Remark The PLLULJDG is reset when it is read-accessed with a PEEK instruction.
Flag symbol
Address
b
b
b
3
2
1
0
P
L
0
0
22H
L
U
L
Detects the state of the unlock FF.
0
Unlock FF = 0 : PLL locked
1
Unlock FF = 1 : PLL unlocked
Fixed to 0.
0
0
*
Hold
Hold
) of the reference frequency f
r
Read/write
R
PD17062
, the content of
r
229
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