NEC PD17062 Datasheet page 144

5 V
V
DD
0 V
CE
Internal pulse
10 Hz
Timer carry FF
set pulse
BTM0CY flag
Program
processing
Program
instruction
Supply voltage Start at address 0
applied on a power-on reset
As shown in Fig. 12-6, the positive-going edge of the internal 10 Hz pulse starts the program at 000H at
a power-on reset.
When the BTM0CY flag is checked at point A, it appears to be reset to 0, thus indicating a power-on reset,
because it is just after the power is turned on.
When a power-on reset occurs, process C is performed to specify the timer carry FF set pulse as 100 ms.
Because the timer carry FF was read-accessed once at point A, the BTM0CY flag is set to 1 at intervals of
100 ms.
Even when the CE pin goes low at point B and high at point C, the program continues updating the clock
while performing process B unless a clock stop instruction has been executed.
Because the CE pin goes from a low to a high at point C, a CE reset occurs at point D, where the timer carry
FF set pulse rises for the second time, thus starting the program at 0000H.
When the BTM0CY flag is checked at point E, a backup (CE reset) is detected because the BTM0CY flag is
already set to 1.
As seen from the timing chart, if the clock is not updated by 100 ms at point E, the clock loses 100 ms each
time a CE reset occurs.
If process A (power failure check) takes longer than 100 ms at point E, the program loses twice a chance
of detecting when the BTM0CY flag is set; therefore, process A must be completed within 100 ms.
To put in another way, checking the BTM0CY flag for power failure must be performed before the timer
carry FF is set after the program starts at 0000H.
144
Fig. 12-6 Timing Chart
A C B B B
# % % % % % %
Timer Timer
incremented incremented
BTM0CY flag detected
Point A
B B B B B B
% % % %
Timer Timer
incre-
incre-
mented
mented
Point B Point C Point D
PD17062
B A B B B
# % %
Start at
Timer
address 0
incremented
on a CE
reset
Timer updated because
the BTM0CY flag has
been detected to be
set to 1
Point E