Timer Carry Flip-Flop (Timer Carry Ff) - NEC PD17062 Datasheet

12.3 TIMER CARRY FLIP-FLOP (TIMER CARRY FF)

The timer carry FF is set to 1 by the positive-going edge of the timer carry FF set pulse specified by the
timer mode select register.
The content of the timer carry FF corresponds to the lowest bit (BTM0CY flag) of the timer carry FF judge
register on a one-to-one basis, and when the timer carry FF is set to 1, the BTM0CY flag is also set to 1 at the
same time.
The BTM0CY flag is reset to 0 by the PEEK instruction when it reads the content of the window register
(Read & Reset).
When the BTM0CY flag is reset to 0, the timer carry FF is also reset to 0 at the same time.
Reading the BTM0CY flag by program can create a timer that operates at intervals of the time specified
in the timer mode select register.
Section 12.3.1 gives an example of a program used to read the BTM0CY flag.
When using the timer carry FF, observe the following point.
A power-on reset disables the timer carry FF from being bet. It cannot be set until the PEEK instruction
is issued to read the content of the BTM0CY flag.
0 is read in when the BTM0CY flag is read-accessed for the first time after a power-on reset. Once it is reset,
the timer carry FF is set to 1 at intervals of the time specified in the timer mode select register.
The timer carry FF also controls the timing of a CE reset.
To put in another way, once the CE pin goes from a low to a high, a CE reset occurs at the same time the
timer carry FF is set.
Therefore, reading the content of the BTM0CY flag at a reset (power-on or CE reset) enables a power failure
check. See Section 12.4 and Chapter 14 for details.
Because the BTM0CY flag is a read-only flag, writing to it with the POKE instruction does not affect the
operation of the device at all. However, an error is reported by the 17K series assembler.
136
PD17062