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(2) Master operation wait in two-wire bus mode
Master operation wait in two-wire bus mode incurs the interruption of transmission. In this mode, when
the timing specified by SIO0WRQ1 and SIO0WRQ0 is set, the shift clock is fixed to the low level.
For example, testing the flag enables the system to determine whether the receiver has returned an
acknowledgement while waiting with the acknowledge wait mode (SIO0WRQ1 = 1, SIO0WRQ0 = 0: Waits
when the shift clock falls with the clock counter set to 9) specified. While waiting in this mode, data to
be transmitted next can be set in the presettable shift register.
Wait is released by writing 1 into the SIO0NWT flag, in exactly the same way as for a slave operation. If
no-wait is specified, this operation is not performed.
(3) Internal clock operation wait in serial I/O mode
This wait mode is almost the same as wait in two-wire bus mode. This wait also incurs the interruption
of transmission. The only difference is that the master operation waits with the shift clock set to low level
in two-wire bus mode while the internal clock operation waits with the shift clock set to the high level in
serial I/O mode.
If serial I/O mode is specified, the clock counter is reset to 0 by performing a data write operation on the
wait register. For this reason, if data wait mode is specified then acknowledge wait mode is respecified,
the clock counter starts counting after being reset to 0 and the shift clock stops at the high level when
the clock counter reaches 9.
This means that, in internal clock operation mode of serial I/O mode, writing data into the wait register
resets the clock counter, after which transmission starts.
If no-wait is specified, the shift clock is output continuously.
(4) External clock operation wait in serial I/O mode
For external clock operation in serial I/O mode, update of the clock counter and shift of the presettable
shift register are prohibited at the timing specified by SIO0WRQ1 and SIO0WRQ0. For example, if data
wait mode is specified, the external clock waits when the clock falls with the clock counter set to 8. And,
the clock counter is subsequently not updated by the shift clock input, nor does the presettable shift
register shift data.
To enable data after waiting, 1 must be written into the SIO0NWT flag as usual. This means that the clock
counter is reset to 0 by writing data into the wait register, after which wait is released.
PD17062
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