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NEC PD17062 Datasheet

Mos integrated circuit 4-bit single-chip microcontroller containing pll frequency synthesizer and image display controller.
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4-BIT SINGLE-CHIP MICROCONTROLLER CONTAINING PLL FREQUENCY
SYNTHESIZER AND IMAGE DISPLAY CONTROLLER
The
PD17062 is a 4-bit CMOS microcontroller for digital tuning systems.
incorporates an image display controller enabling a range of different displays, together with a PLL frequency
synthesizer.
The CPU has six main functions: 4-bit parallel addition, logic operation, multiple bit test, carry-flag set/
reset, powerful interrupt, and a timer.
The device contains a user-programmable image display controller (IDC) for on-screen displays. The
different displays can be controlled with simple programs.
The device also has a serial interface function, many input/output (I/O) ports controlled by powerful I/O
instructions, and 6-bit pulse width modulation (PWM) output for a 4-bit A/D converter and D/A converter.
FEATURES
• 4-bit microcontroller for digital tuning system
• Internal PLL frequency synthesizer: With prescaler
PB595
• 5 V 10%
• Low-power CMOS
• Program memory (ROM): 8K bytes (16 bits 3968
steps)
• Data memory (RAM): 4 bits
• 6 stack levels
• 35 easy-to-understand instruction sets
• Support of decimal operations
• Instruction execution time: 2 s (with an 8-MHz
crystal)
• Internal D/A converter: 6 bits
• Internal A/D converter: 4 bits
• Internal horizontal synchronizing signal counter
• Internal commercial power frequency counter
• Internal power-failure detector and power-on reset
circuit
Document No. IC-3560
(O.D. No. IC-8937)
Date Published January 1995 P
Printed in Japan
DATA SHEET
336 words
4 (PWM output)
6
The information in this document is subject to change without notice.
MOS INTEGRATED CIRCUIT
• Internal image display controller (IDC) (user-pro-
grammable)
Number of characters in display: Up to 99 on a
single screen
Display configuration: 14 rows
Number of character types: 120
Character format: 10
15 dots (rimming possible)
Number of colors: 8
Character size: Four sizes in each of the horizontal
and vertical dimensions
Internal 1H circuit for preventing vertical deflection
• Internal 8-bit serial interface (One system with two
channels: three-wire or two-wire)
• Interrupt input for remote-controller signals (with
noise canceler)
• Many I/O ports
Number of I/O ports
: 15
Number of input ports : 4
Number of output ports: 8
PD17062
The single-chip device
19 columns
©
1995

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   Summary of Contents for NEC PD17062

  • Page 1

    4-BIT SINGLE-CHIP MICROCONTROLLER CONTAINING PLL FREQUENCY SYNTHESIZER AND IMAGE DISPLAY CONTROLLER PD17062 is a 4-bit CMOS microcontroller for digital tuning systems. incorporates an image display controller enabling a range of different displays, together with a PLL frequency synthesizer. The CPU has six main functions: 4-bit parallel addition, logic operation, multiple bit test, carry-flag set/ reset, powerful interrupt, and a timer.

  • Page 2: Pwm

    Reference frequency : 6.25, 12.5, 25 kHz Charge pump : Error-out output Phase comparator : Capable of unlock detection by a program Power-on reset Reset by the CE pin With power-failure detection function 5 V 10% PD17062 19 columns C bus compatible)

  • Page 3

    BLUE GREEN to P0D to P1A to P1B to P1C TMIN SYNC PD17062 : Port 0D : Port 1A : Port 1B : Port 1C : Character signal output : Shift clock input/output : Shift clock input/output : Serial data input/output...

  • Page 4

    64-pin plastic QFP (14 14 mm) /ADC PD17062GC- -3BE PD17062 /TMIN /HSCNT /ADC SYNC SYNC BLANK BLUE...

  • Page 5

    BLUE BLANK /SDA /SCL Serial /SCK /TMIN /HSCNT Hsync Counter Timer Controller /ADC /ADC /ADC /ADC /ADC 4 bits (Including VRAM) SYSREG 3968 16 bits Interrupt (Including CROM) Controller Instruction Decoder Program Counter Peripheral Stack 6 12 bits PD17062 Reset...

  • Page 6: Table Of Contents

    CONFIGURATION AND FUNCTIONS OF THE COMPONENTS OF THE ALU BLOCK ... ALU OPERATIONS ... NOTES ON USING THE ALU ... SYSTEM REGISTER (SYSREG) ... ADDRESS REGISTER (AR) ... WINDOW REGISTER (WR) ... BANK REGISTER (BANK) ... MEMORY POINTER ENABLE FLAG (MPE) ... CONTENTS PD17062...

  • Page 7

    DATA BUFFER AND PERIPHERAL REGISTERS ... 10.6 PRECAUTIONS WHEN USING DATA BUFFERS ... 104 11. INTERRUPT ... 106 11.1 INTERRUPT BLOCK CONFIGURATION ... 106 11.2 INTERRUPT FUNCTION ... 108 11.3 INTERRUPT ACCEPTANCE ... 111 11.4 OPERATIONS AFTER INTERRUPT ACCEPTANCE ... 116 PD17062...

  • Page 8

    STATUS REGISTER ... 207 16.4 WAIT REGISTER ... 209 16.5 PRESETTABLE SHIFT REGISTER (PSR) ... 214 16.6 SERIAL INTERFACE INTERRUPT SOURCE REGISTER (SIO0IMD) ... 215 16.7 SHIFT CLOCK FREQUENCY REGISTER (SIO0CK) ... 216 PIN, V PIN) ... 121 SYNC PD17062...

  • Page 9

    LIST OF INSTRUCTION SETS ... 279 22.4 BUILT-IN MACRO INSTRUCTIONS ... 281 23. RESERVED SYMBOLS FOR ASSEMBLER ... 282 23.1 SYSTEM REGISTER (SYSREG) ... 282 23.2 DATA BUFFER (DBF) ... 282 23.3 PORT REGISTER ... 283 23.4 REGISTER FILES ... 284 PD17062...

  • Page 10

    23.5 PERIPHERAL HARDWARE REGISTER ... 286 23.6 OTHERS ... 286 24. ELECTRICAL CHARACTERISTICS ... 287 25. PACKAGE DRAWINGS ... 289 26. RECOMMENDED SOLDERING CONDITIONS ... 291 APPENDIX DEVELOPMENT TOOLS ... 292 PD17062...

  • Page 11: Pins

    0. Used to connect a crystal. An 8-MHz crystal is used. Description CMOS push-pull N-ch open drain CMOS tristate CMOS push-pull PD17062 Output type At power-on reset Undefined — Input Undefined — —...

  • Page 12

    • SCL: Serial clock input/output • SDA: Serial data input/output Description N-ch open-drain CMOS push-pull CMOS push-pull CMOS push-pull CMOS push-pull N-ch open-drain CMOS push-pull (Other than P0A PD17062 Output type At power-on reset Undefined Input Low level Low level — Input — Input Input —...

  • Page 13

    — No connection. The pins are not connected to the internal circuit of the device. They can be used as desired. Description Output type PD17062 At power-on reset — Input...

  • Page 14: Equivalent Circuits Of The Pins

    , P0B /SI) P1B (P1B , P1B , P1B , P1B P1C (P1C /ADC , P1C , P1C P0A (P0A /SCL, P0A /SDA) A/D converter (only for P1C/ADC) RESET signal (except for P1C) Read instruction (only for P1C) (I/O) PD17062...

  • Page 15

    PWM (PWM , PWM , PWM , PWM P1A (P1A , P1A , P1A , P1A P0D (P0D /ADC , P0D /ADC , P0D /ADC (Output) (Output) , P0D /ADC A/D Converter (Input) High on-state resistance A/D converter selection signal PD17062...

  • Page 16

    /HSCNT /TMIN P-ch N-ch P-ch N-ch Port PD17062 Port Horizontal synchronizing signal counter Timer/counter...

  • Page 17

    , INT , CE SYNC SYNC PD17062 (Hysteresis input) (Input)

  • Page 18: Program Memory (rom)

    MOVT, PUSH, and POP instructions. Fig. 2-1 Configuration of Program Memory Address 0 000H Page 0 0 7FFH 0 800H Page 1 (area that can be used as CROM) 0 F7FH Program memory (ROM) 16 bits PD17062 16 bits). 3968 steps...

  • Page 19: Functions Of Program Memory

    If a predetermined condition is satisfied, the interrupt function transfers control to a specified address (vector address) irrespective of the current program flow. These program flows are controlled by the program counter (PC), which specifies program memory addresses. PD17062...

  • Page 20: Branching A Program

    0000H and 0F7FH. 2.4.2 Indirect Branch The indirect branch instruction uses the eight-bit data of an address register to specify the destination address. The destination of the indirect branch instruction is limited to addresses between 0000H and 00FFH. See Section 8.1. PD17062...

  • Page 21

    (b) Indirect branch (BR @AR) Address 0000H Label: Instruction 0010H 0085H 0500H 07FFH 0800H 0F7FH 0 1100 101 0000 0000 PD17062 Program memory (Machine code) MOV AR0, #5H MOV AR1, #8H Page 0 MOV AR0, #0H MOV AR1, #1H Page 1...

  • Page 22

    The indirect subroutine call instruction (CALL @AR) uses the 8-bit data in an address register (AR) to specify the address of a subroutine to be called. The instruction can call a subroutine from a program memory address between 0000H and 00FFH. See Section 8.1. PD17062...

  • Page 23

    (b) If the first address of the subroutine is in page 1 Address Program memory 0 000 H Label: Instruction CALL SUB1 SUB1:BR SUB2 0 7FF H Page 0 0 800 H 0 890 H SU B 2: CALL SUB1 Page 1 0 F7F H PD17062...

  • Page 24: Table Reference

    ; program. ; As a label type, 0005H is assigned to LOOP2. ; The numeric value of the operand is converted to a label type. It is recommended that this method not be used to reduce the number of bugs. PD17062...

  • Page 25: Program Counter (pc)

    If a power-on reset or a CE reset is performed, the program counter is reset to address 0. Table 3-1 Vector Addresses upon Interrupt Occurrence Priority Fig. 3-1 Program Counter 12 bits Interrupt cause Vector address Internal timer SYNC Serial interface PD17062...

  • Page 26: Stack

    Fig. 4-1 Structure of Stack Pointer Table 4-1 Behavior of Stack Pointer CALL addr CALL @AR MOVT DBF, @AR PUSH AR Interrupt acceptance RETSK MOVT DBF, @AR POP AR RETI (SPb (SPb (SPb Instruction Stack pointer value SP – 1 SP + 1 PD17062...

  • Page 27: Address Stack Registers (asrs)

    If a power-on reset is performed, the contents of the interrupt stack registers become undefined. Even if a CE reset is performed or a clock stop instruction is executed, however, the contents of the interrupt stack registers remain as is. PD17062...

  • Page 28

    Fig. 4-3 Structure of Interrupt Stack Registers Fig. 4-4 Not defined Not defined Not defined is applied. Interrupt A BANKSK0 IXESK0 BANKSK1 IXESK1 Behavior of Interrupt Stack Registers Not defined Interrupt B RETI RETI PD17062 Not defined Not defined...

  • Page 29: Data Memory (ram)

    1H and column address AH is referred to as the data memory location having address 1AH. One address consists of four bits of memory. These four bits are called a nibble. Data memory is divided into the blocks described in Sections 5.1.1 to 5.1.5, according to function. PD17062...

  • Page 30

    (4 bits) (4 bits) Fixed (4 bits) (4 bits) (4 bits) at 0 (4 bits) (4 bits) (4 bits) (4 bits) Fig. 5-1 Data Memory Structure BANK0 System register BANK1 System register BANK2 System register PD17062 DBF3 DBF2 DBF1 DBF0...

  • Page 31

    Fig. 5-3 Structure of the Data Buffer Address Symbol System register (SYSREG) Index register (IX) Window Bank register register Data memory row (WR) (BANK) address pointer (MP) Data buffer (DBF) DBF3 DBF2 DBF1 DBF0 PD17062 General-purpose Program register pointer status word (RP) (PSWORD)

  • Page 32

    Fig. 5-4 Structure of the General-Purpose Register (GR) Column address BANK0 BANK1 BANK2 SYSREG SYSREG SYSREG PD17062 General-purpose register Area specifiable as general-purpose register Pointed to by general-purpose register pointer (RP) in system register. The same register is allocated for each bank.

  • Page 33

    General-purpose data memory consists of a total of 336 words, with 112 words in each of BANK0 to BANK2. 5.1.6 Unmounted Data Memory As shown in Fig. 5-6, nothing is assigned to bit 0 of address 72H in BANK1 of the port registers. For an explanation of this address, see Section 5.3.2. Port register Fixed at 0 PD17062...

  • Page 34: Functions Of Data Memory

    ; 7H, or address 17H of BANK0. ; Transfer the contents of data memory address 36H to ; the general-purpose register location having column ; address 7H. ; In this instruction, the general-purpose register ; location is address 17H of BANK0. PD17062...

  • Page 35

    The bank and the row address for the general-purpose register are specified by the general-purpose register pointer in the system register. The general-purpose register pointer of the PD17062 always specifies BANK0. For example, if the general-purpose register pointer is set to 0, 16 nibbles at row address 0 of BANK0, or addresses 00H to 0FH of BANK0, are allocated as the general-purpose register.

  • Page 36

    Table 5-1 Data Memory Manipulation Instructions Operation Comparison Transfer Decision Function Instruction Addition ADDC Subtraction SUBC Logical operation SKGE SKLT SKNE PD17062...

  • Page 37

    P1A1 P1A0 P1B3 P1B2 Port1B P1B1 P1B0 P1C3 P1C2 Port1C P1C1 P1C0 – PD17062 Input or output Input and output (bit I/O) Input and output (bit I/O) Output Input Output Input and output (bit I/O) Input and output (group I/O)

  • Page 38: Notes On Using Data Memory

    ; Address 2FH of BANK0 is defined symbolically in ; M02F as a memory-type address. ; address by using .MD.. However, the use of this type of ; instruction should be avoided to reduce the ; likelihood of bugs arising. PD17062...

  • Page 39

    Column address Assembler built-in macro instruction BANK M1, M2, and M3 are defined symbolically in banks, but are for BANK1 in this program. Thus, all of these three instructions write 0s to data memory address 15H in BANK1. PD17062 for different...

  • Page 40: General-purpose Register (gr)

    This enables an operation or transfer to be performed between data memory locations by the execution of a single instruction. Like other data memory, the general-purpose register can be controlled using a data memory manipulation instruction. 4 bits) having the same row address in data memory space can PD17062...

  • Page 41

    0 1 2 3 4 5 6 7 8 9 A B C D E F General-purpose register (16 words) BANK0 System register BANK1 System register BANK2 System register PD17062 General-purpose register allocated when RP = 010B. The same system register is viewed.

  • Page 42: Address Generation For General-purpose Register And Data Memory In Individual Instructions

    MPE = 0: (BANK, m m, @r if MPE = 1: (m) if MPE = 0: (m) RORC Right shift, including a carry Generated address Bank Row address (RP) (0000B) (BANK) PD17062 Operation , (r)) (MP, (r)) (BANK, m , (r)) Column address...

  • Page 43

    See Fig. 6-2. Fig. 6-2 Execution of Instructions in Example 1 ; RP 0000000B; The general-purpose register is allocated in row ; address 0H in BANK0. Column address General-purpose register ADD 04H, 56H BANK0 System register 0000000B PD17062...

  • Page 44

    ; address 0H in BANK0. Column address General-purpose register @ 04H, 56H BANK0 System register 0000000B; The general-purpose register is allocated in row ; address 0H of BANK0. 0000100B; The general-purpose register is allocated in row ; address 4H of BANK0. PD17062...

  • Page 45

    3, the operation can be completed simply by executing a storage instruction. Fig. 6-4 Execution of Instructions in Example 3 Column address BANK0 System register BANK1 System register BANK2 System register PD17062 RP = 0000000B RP = 0000100B...

  • Page 46: Notes On Using The General-purpose Register

    R1 and R2 are assigned the same column address. 0.34H 0.32H ; RP 0000010B ; BANK0 ; The address of the general-purpose register is coded as 04. R1 and M1 are defined as memory-type addresses, and are assigned addresses 04H and 32H of BANK0, respectively. PD17062 because...

  • Page 47

    Column address General-purpose register BANK0 04H, System register PD17062 RP = 0000010B...

  • Page 48: Arithmetic Logic Unit (alu) Block

    Data bus Temporary Program status storage storage word register B • Arithmetic operation • Logic operation • Bit discrimination • Comparative discrimination • Rotation • Transfer Decimal conversion PD17062 Detecting a carry, borrow, or zero Setting decimal calculation or result storage...

  • Page 49: Configuration And Functions Of The Components Of The Alu Block

    Table 7-1 lists the operations performed by the ALU when instructions are executed. Table 7-2 shows the data memory address modification by the index register and data memory row address pointer. Table 7-3 lists the converted decimal data used in decimal operations. PD17062...

  • Page 50: Alu Operations

    Retains the previous state. state. Retains the Not changed Retains the previous state. previous state. Value of b the general- Not changed Retains the previous state. purpose register PD17062 Address modification Index Memory pointer Provided provided Provided provided Provided provided Provided provided provided...

  • Page 51

    : Contents addressed by Data memory address specified with m Column Bank address address BANK Same as above BANK Logical Same as above and m PD17062 Indirect transfer address specified with @r Column Bank address address BANK BANK Logical IXH, IXM...

  • Page 52

    –10 1101B –9 –8 1110B 1111B –7 1100B –6 1101B –5 1010B –4 –3 1011B –2 1100B 1101B –1 PD17062 Decimal subtraction Operation result result 0000B 0000B 0001B 0001B 0010B 0010B 0011B 0011B 0100B 0100B 0101B 0101B 0110B 0110B 0111B...

  • Page 53: Notes On Using The Alu

    (2) The result of subtraction is between 0 and 9 or –10 and –1 in decimal. If a decimal operation exceeding the above ranges is performed, the CY flag is set, resulting in a value greater than or equal to 1010B (0AH). PD17062...

  • Page 54: System Register (sysreg)

    0 0 0 0 0 0 0 0 System register Index register (IX) Window Bank Data memory register register row address (WR) (BANK) pointer (MP) BANK P 0 0 0 0 (MP) PD17062 General- Program purpose status register word pointer (PSWORD) (RP) (IX) 0 0 0 0...

  • Page 55: Address Register (ar)

    AR3 and AR2 of PD17062 are fixed at 0. Hence, the program address that can be specified by the address register is the 256 steps of 0000H-00FFH.

  • Page 56: Bank Register (bank)

    MPL. When the MPE is reset, the instruction is executed with same row address. However, the address specified by the MPL is the row address of the currently specified bank. Bank request (BANK) Data memory bank BANK0 BANK1 BANK2 Not to be set PD17062...

  • Page 57: Index Register (ix) And Data Memory Row Address Pointer (mp)

    This means that the seven high-order bits of the index register and data memory row address pointer are shared. The four high-order bits of the index register, i.e., the four high-order bits of the data memory row address pointer (7AH b , 7BH b ), of PD17062 are fixed at 0. PD17062...

  • Page 58

    All data memories are subject to modification by the index register and data memory row address pointer. The following instructions are not subject to modification by the index register. MOVT DBF, @AR PUSH PEEK WR, rf POKE rf, WR DBF, P p, DBF addr RORC CALL addr CALL RETSK RETI STOP HALT PD17062...

  • Page 59

    ; Contents of index register IXH ; Bits b IXM ; Bits b ; Bits b ; Data memory row address pointer (MP) ; Contents of data memory row address pointer PD17062 Indirect transfer address specified by @r Column Bank address address (BANK)

  • Page 60

    (in the above case, 3EH) specified by the contents (in the above case, 0EH) of general-purpose register r to m (See Example 3 in Fig. 8-3). The (transfer) source and (transfer) destination are exactly opposite to those in example 2. ; 05H ; Register indirect transfer ; 0BH PD17062...

  • Page 61

    Address generation of example 2 @ r, 05H 34H Column address Specifies the destination column address Example 3. MOV 34H, @0BH Bank Row address (@ r) Same as M PD17062 General- purpose Specifies the source register column address Column address Contents of R...

  • Page 62

    Example 2. When the row address of the general-purpose register is 0 for BANK0 MPL, #0101B MPH, #1000B 0BH, #0EH 3AH, @05H (See Example 2 in Fig. 8-4.) ; MP 00101B ; MPE ; 05H ; Register indirect transfer ; MP 00101B ; MPE ; 0BH PD17062...

  • Page 63

    The bank and row address are set to 000101B, the value of the data memory row address pointer. Bank Row address 0 0 0 0 1 0 1 (@ r) Value of MP PD17062 Specifies the source column address Column address Contents of R...

  • Page 64

    ; is 7FH. #0111B ; Is row address 7 reached? ; LOOP if not 7 ; Specifies the next bank without clearing row address 7. #1000B ; Were banks cleared up to BANK2? #0001B ; ; LOOP unless cleared PD17062...

  • Page 65

    Fig. 8-5 Data Memory Address Modification with IXE = 1 Column address ADD r, m Specified by IX PD17062 General- purpose register...

  • Page 66: General-purpose Register Pointer (rp)

    The general-purpose register pointer points to the bank and row address of the general-purpose register. However, since RPH of the PD17062 is fixed at 0, only RPL (3 bits) can be specified. This means that 0 to 7 can be specified as a register pointer. Hence, in the PD17062, the row address of the general-purpose register can be specified anywhere within BANK0.

  • Page 67: Register File (rf)

    64 nibbles (00H-3FH) and addresses 40H-7FH of the currently selected bank of data memory to the low-order 64 nibbles (40H-7FH). This means that 40H-7FH of each bank of data memory belongs to both the data memory address space and the register file address space. In the assembler, the control register file is allocated to 80H-BFH. PD17062...

  • Page 68

    0 0 0 PLL-unlock- flip-flop judge register 0 0 0 PLL-unlock- flip-flop sensibility select register R /W PD17062 CE pin level judge register mode Basic timer 0 select carry flip-flop register judge register Port 1C group I/O select register...

  • Page 69

    Serial I/O0 wait control register Serial I/O0 status judge register Serial I/O0 Serial I/O0 interrupt clock select mode register register PD17062 Interrupt- level judge register Interrupt edge selection register Interrupt enable register Interrupt request register...

  • Page 70

    Selects the pulse width of 0: Accepts with edge interrupt accept pulse width 1: 200 s 2: 400 s 3: 2 ms of the INT 4: 4 ms PD17062 At reset Set value Operation 0 0 * 0 1 1...

  • Page 71

    Detects the unlock flip-flop state Locked state Fixed at 0 1.25 Sets the set delay time for the unlock flip-flop 1.5 s 3.75 s 0.5 s PD17062 At reset Set value Falling edge Falling edge Interrupt enabled Interrupt request made 0 –...

  • Page 72

    Sets and detects acknowledge (I C bus method) Sets and detects 0 and 1 Sets the wait permission Permitted Data Sets the wait mode wait wait PD17062 At reset Set value 1: AD1 3: AD3 5: AD5 ** * * > V Output...

  • Page 73

    Gate counter gate close open Detects open/close of the H counter Gate close SYNC Fixed at 0 PD17062 At reset Set value Resets when the contents of the clock counter become 8 Resets when the contents of the clock counter...

  • Page 74

    Fixed at 0 Sets the DMA mode permission Not permitted Fixed at 0 Fixed at 0 BANK0 Selects the CROM bank (0800H-0BFFH) Fixed at 0 Display on Turns the IDC display on/off PD17062 At reset Set value Permitted BANK1 (0C00H-0F7FH) Display off...

  • Page 75: Idcdmaen

    (SPb (SPb (SPb DMA prohibited mode (instruction cycle = 2 s) DMA mode (instruction cycle = 12 s) SP (stack pointer) Level 6 Level 5 Level 4 Level 3 Level 2 Level 1 At reset Not to be set PD17062...

  • Page 76: Ce (07h, B )

    Serial I/O mode : External clock operation 2-wire bus mode : Master operation Serial I/O mode : Internal clock operation Setting of serial interface mode Serial I/O mode 2-wire bus mode Setting of serial interface channel Selects CH0 Selects CH1 PD17062...

  • Page 77: Btm0md (09h)

    BTM0CK0 Time base setting TIMER INT 5 ms 100 ms 20 ms 20 ms 5 ms 5 ms Zerocross setting Zerocross off Zerocross on PD17062 TIMER CARRY Internal 100 ms Internal Internal 5 ms Internal Internal 100 ms Internal Internal...

  • Page 78: Intnc (0fh, B )

    Setting of horizontal synchronizing signal counter Gate close Gate open Gate open (1.69 ms interval) Not to be set Both bits are fixed at 0. Input confirmation of gate open/close of horizontal synchronizing signal counter Gate close Gate open PD17062...

  • Page 79: Pll Reference Mode Selection Register (13h)

    INTNCMD0 Setting of INT pin acceptance pulse width Edge (no noise canceler) 200 s 400 s 2 ms 4 ms Fixed at 0 PD17062 setting 6.25 kHz 12.5 kHz 25 kHz PLL disabled Not to be set Fixed at 1...

  • Page 80: Timer Carry (17h)

    Interrupt occurs at the falling edge of the INT Interrupt occurs at the rising edge of the V Interrupt occurs at the falling edge of the V PD17062 Serial I/O mode Does not wait Waits when the contents of the...

  • Page 81: A/d Convertor Control (21h)

    P0D select, shared with P1D select, shared with P0D select, shared with P0D No corresponding channel (not to be set) PLLUL Detects the unlock flip-flop state Unlock flip-flop = 0: PLL locked Unlock flip-flop = 1: PLL unlocked PD17062...

  • Page 82: Port1c I/o Setting (27h)

    Resets when the contents of the clock counter become 0 or 1 Sets when the contents of the clock counter become 9 8 clock detection Resets when the contents of the clock counter become 0 or 1 Sets when the contents of the clock counter become 8 PD17062...

  • Page 83: Interrupt Permission Flag (2fh)

    Interrupt from the V SYNC Interrupt from the V SYNC Interrupt from the serial interface disabled Interrupt from the serial interface enabled CROMBNK CROM address setting CROM address 0800H-0BFFH CROM address 0C00H-0F7FH PD17062 pin disabled pin enabled pin disabled pin enabled...

  • Page 84: Idcen (31h)

    Setting of the delay time of the reference frequency f divided frequency f required for setting the unlock flip-flop 1.25 to 1.5 s or more 3.5 to 3.75 s or more 0.25 to 0.5 s or more Unlock flip-flop disable (always set) Fixed at 0 PD17062...

  • Page 85: P1bbion (35h)

    P0BBIOn specifies the PORT0B I/O. When P0BBIOn is set to 0, PORT0B becomes an input port. When P0BBIOn is set to 1, PORT0B becomes an output port. P0BBIO3 P0BBIO2 P1BBIO1 P1BBIO0 P0BBIO1 P0BBIO0 PD17062 I/O setting input port output port I/O setting input port output port I/O setting...

  • Page 86: P0abion (37h)

    Interrupt request generated at rising edge of the 8th bit of the shift clock Interrupt request generated at rising edge of the 7th bit of the shift clock immediately after the start condition is detected Interrupt request generated when the stop condition is detected PD17062 input port output port input port...

  • Page 87: Shift Clock Frequency Setting (39h)

    If 0 is written, the interrupt hold status can be released. The IRQNC flag becomes 0 upon reset. Flag name IRQNC IRQBTM0 IRQVSYN IRQSIO0 SIO0CK1 SIO0CK0 Internal clock frequency Fixed at 0 Bit position Interrupt source Clock timer SYNC Serial interface PD17062 100 kHz 200 kHz 500 kHz 1 MHz...

  • Page 88: Data Buffer (dbf)

    16 bits in a 4-word 4-bit configuration. Because the data buffer is mapped to data memory, it can be operated by data memory instructions. Data buffer Fig. 10-1 Data Buffer Map Column address Data memory BANK0 BANK1 BANK2 System register PD17062...

  • Page 89

    As shown in Fig. 10-2, the data buffer consists of 16 bits. Bit b and bit b of data memory address 0CH bit 3 is the MSB. Address Data memory Symbol Data buffer Data of data memory address 0FH is the LSB, Fig. 10-2 Data Buffer Structure DBF3 DBF2 Data PD17062 DBF1 DBF0...

  • Page 90: Functions Of Data Buffer

    Fig. 10-3 Relationship Between Data Buffer, Peripheral Hardware, and Memory Data buffer Internal Program memory (ROM) Table referencing Constant data Peripheral hardware Peripheral address Image display controller (IDC) A/D converter Serial interface Horizontal synchronizing signal counter 6-bit D/A converter 05H-08H Address register (AR) PLL frequency synthesizer PD17062...

  • Page 91: Data Buffer And Table Referencing

    Because the address register (AR) has only eight valid bits, program memory available for table reference is limited to 256 steps from address 0000H to address 00FFH. See also Chapter 4 and Section 8.1. DBF0 PD17062 Program memory (ROM) Constant data...

  • Page 92

    ; Transfers the contents of data buffer to Port0A (70H), ; Port0B(71H), and Port0C (72H) port data registers. ; Increments the contents of data register by one. ; Writes 0 in AR0 when the value of AR0 reaches 0CH. PD17062...

  • Page 93: Data Buffer And Peripheral Hardware

    • When a read (GET) instruction is executed for a write only (PUT only) peripheral register, an undefined value is returned. • When a write (PUT) instruction is executed for a read only (GET only), it has no effect. Be careful when using a 17K series assembler and emulator. For details, see Section 10.6. PD17062...

  • Page 94

    I/O bits instruction PUT/GET ADCR PUT/GET PUT/GET PUT/GET PUT/GET PLLR PUT/GET PD17062 Function Valid Explanation bits Sets the image display controller display start position. Sets the AD converter comparison voltage x – 0.5 Sets the serial out data and reads the serial in data.

  • Page 95

    Of the 8-bit data in the data buffer, the status of each bit that does not correspond to a valid bit in the peripheral register is “Don’t care”. Data buffer DBF1 DBF0 Peripheral register Valid bits PD17062 to bit Don't care (Can be any value) 0 or unpredictable...

  • Page 96

    The valid bits of each peripheral register are reset as follows: Power-on Clock-stop Data buffer DBF1 DBF0 Peripheral register Valid bits Reset Valid bit state Unpredictable Previous state held Previous state held PD17062 0 or unpredictable The value of the peripheral register is read without alteration. 0 or unpredictable...

  • Page 97: Data Buffer And Peripheral Registers

    IDC start position setting register DBF1 DBF0 Transfer data Peripheral register Valid data D7 D6 D5 D4 D3 D2 D1 D0 PD17062 Peripheral Symbol Peripheral hardware address Image display IDCORG controller IDC display position setting D7 to D4: Horizontal start position...

  • Page 98

    Don't care Don't care Name A/D converter data register DBF1 DBF0 Transfer data Peripheral register Valid data A/D converter comparison voltage V Fixed at 0 PD17062 Peripheral Symbol Peripheral hardware address ADCR A/D converter setting = 0 V x - 0.5...

  • Page 99

    Peripheral register Valid data Serial out data write and serial in data read D7 D6 D5 D4 D3 D2 D1 D0 Serial out data Serial in data PD17062 Peripheral Symbol Peripheral hardware address SIO0SFR Serial interface D7 D6 D5 D4 D3 D2 D1 D0...

  • Page 100

    Fig. 10-7 HSYNC Data Register Functions Name Data buffer Symbol DBF3 DBF2 Address Data Don't care Don't care Name HSYNC counter data register DBF1 DBF0 Transfer data Peripheral register Valid data Horizontal synchronizing signal count PD17062 Peripheral Symbol Peripheral hardware address Horizontal synchronizing signal counter...

  • Page 101

    , PWM , PWM , and PWM DBF1 DBF0 Transfer data Peripheral register Valid data Set the PWM output duty of each pin. PD17062 ). Because the duty cycle Peripheral Symbol Peripheral hardware address PWMR0 PWMR1 PWMR2 PWMR3 x + 0.75...

  • Page 102

    Address Data Transfer data Name Address register DBF1 DBF0 Peripheral register Valid data Address register data write and read PD17062 Peripheral Symbol Peripheral hardware address Address register Name Address register Symbol Address Data The eight high-order bits of the address...

  • Page 103

    256 (0100H) - 1 (0FFFFH) Fig. 10-10 PLL Data Register DBF1 DBF0 Peripheral register PLL frequency synthesizer frequency division ratio Not to be set. Frequency division ratio N:N = x PD17062 Peripheral Symbol Peripheral hardware address PLL frequency PLLR synthesizer...

  • Page 104: Precautions When Using Data Buffers

    Writing to a read only register does not change its contents and does not generate an error. Reading from an unused address returns an unpredictable value. Writing to an unused address does not change its contents and does not generate an error. PD17062...

  • Page 105

    ; addresses are directly specified by 02H and 03H. How ; ever, to reduce program bugs, this method should be ; avoided. ; Assigns SIO0DATA to 03H using a symbol definition ; instruction. ; If reserved word SIO0SFR is used, symbol definition is ; unnecessary. PD17062...

  • Page 106: Interrupt

    V pin, and serial interface. The interrupt enable flip- SYNC flip-flop detects an interrupt request, the IP PD17062 flip-flop, IP flip-...

  • Page 107

    IPBTM0 IRQBTM0 Timer IPNC IRQNC Interrupt request processing block Stack pointer (SP) Stack pointer Program counter Address Symbol Flag symbol Interrupt enable flip-flop INTE DI or EI instruction PD17062 Address stack register ASR0 ASR1 ASR5 System register BANK Interrupt stack...

  • Page 108: Interrupt Function

    These flags are reset to 0 at power-on reset, clock stop, or CE reset. pin, timer, V pin (rising or falling edge of the signal applied to PD17062 pin, timer, V pin, and serial SYNC pin), pin, and serial interface.

  • Page 109

    (vector address) of the program memory for the source of the accepted interrupt. Table 11-1 lists the vector addresses corresponding to the interrupt sources. Table 11-1 Interrupt Vector Addresses Interrupt source Vector address Timer SYNC Serial interface PD17062...

  • Page 110

    The contents of the interrupt stack are restored in the bank register and index enable flag in the system register by executing the RETI instruction. The RETI instruction is exclusively used to return control from the interrupt processing routine. See also Chapter 4. PD17062...

  • Page 111: Interrupt Acceptance

    (e.g., IPNC flag for the IRQNC flag) is set 1 when pin > serial interface SYNC is executed according to the priority given by the interrupt PD17062 pin), each type of...

  • Page 112

    IRQNC resetting START Timer SYNC Interrupt Interrupt request? request? IRQBTM0 setting IRQVSYN setting IPBTM0=1? IPVSYN=1? IRQBTM0 resetting IRQVSYN resetting Interrupt acceptance PD17062 Serial interface Interrupt request? IRQSIO0 setting IPSIO0=1? EI state? IRQNC= IPNC=1? IRQBTM0= IPBTM0=1? IRQVSYN= IPVSYN=1? IRQSIO0= IPSIO0=1 IRQSIO0 resetting...

  • Page 113

    See Section 11.4 for details. Because the interrupt request flag is set to 1 regardless of the EI instruction and interrupt permission flags, an interrupt request can be identified by detecting an interrupt request flag using the program. PD17062...

  • Page 114

    Interrupt permission Interrupt processing period Interrupt acceptance MOVT DBF, POKE @AR skip INTPM, WR instruction Interrupt acceptance Interrupt POKE cycle WR, #0001B INTPM, WR Interrupt holding period Interrupt acceptance PD17062 routine Interrupt cycle Interrupt processing routine Interrupt processing routine...

  • Page 115

    SYNC Interrupt POKE WR, #0101B INTPM, WR cycle pin interrupt holding period pin interrupt processing SYNC pin interrupt acceptance SYNC PD17062 pin) are used SYNC Interrupt cycle SYNC interrupt processing pin interrupt acceptance Interrupt cycle pin interrupt processing...

  • Page 116: Operations After Interrupt Acceptance

    The processing in (1) to (3) above is executed during one instruction cycle of the RETI instruction. The only difference between the RETI instruction and subroutine return instruction RET or RETSK is in the restoration of the contents of the bank register or index enable flag in (2) above. PD17062 of the...

  • Page 117

    RETI instruction. The EI instruction sets the interrupt enable flip-flop to 1 after the next RETI instruction is executed. Therefore, control is returned to the program before an interrupt is accepted, then the program enters an interrupt permitted state. PD17062...

  • Page 118

    Data saved by software is not reset after being saved. Program status words such as the BCD flag, compare flag, carry flag, zero flag, and memory pointer enable flags keep their preacceptance values. Initialize these program status words if necessary. PD17062...

  • Page 119: Interrupt Processing Routine

    Restores the contents of the general register-purpose pointer. RPL, M048 Restores the contents of the saved window register. The EI instruction permits an interrupt (INTE setting) after the next RETI instruction is executed. Restoration by the BANK or IXE hardware PD17062...

  • Page 120

    Fig. 11-4 Saving the System or Control Register Using the Window Register Numbers correspond to the numbers in the program example. Column address Data memory BANK0 Save area ( ) # POKE M048, WR AR1 AR0 WR BTM0CK Control register Register file PD17062 & Specify the general- purpose register.

  • Page 121: External Interrupts

    Pin and INT Pin Configurations Interrupt Interrupt edge select pin level judge (INTEDGE) (INTJDG) 1 FH 0 FH INTNC latch Edge detection IEGNC flip-flop INTVSYN latch Edge detection IEGVSYN flip-flop PD17062 or V pin. SYNC Interrupt request block IRQNC IRQVSYN...

  • Page 122

    Flag values IEGNC and V pins are input to the INTNC and INTVSYN latches as shown SYNC Active edges of interrupt request pins INTVSYN Rise Rise Fall Fall PD17062 or V pin. SYNC pin as shown SYNC Rise Fall Rise Fall...

  • Page 123: Internal Interrupt (timer, Serial Interface)

    The serial interface interrupt function can issue an interrupt request when a serial out or serial in operation terminates. Therefore, interrupt requests are mainly issued by the serial clock. See Chapter 16 for details. or V Whether interrupt SYNC request is issued Not issued High Issued Issued High Not issued PD17062 IRQNC flag No change No change...

  • Page 124: Multiple Interrupts

    (2) Interrupt level restriction by an interrupt stack (3) Interrupt level restriction by the address stack register (4) System or control register saving See Sections 11.9.1 to 11.9.4 for details. Fig. 11-6 Example of Multiple Interrupts Main routine MAIN Interrupt level 1 Interrupt level 2 PD17062...

  • Page 125

    However, if the bank register and index enable flag are fixed in a main routine permits interrupts and multiple interrupts have clear priorities as shown in Fig. 11-8, multiple interrupts of two levels or more can be used by using subroutine return instruction RET. PD17062...

  • Page 126

    At interrupt stack, the device operation is the sweep-off type and the emulator operation is the rotation type. Use the RET instruction as the last restoration instruction when using multiple interrupts of more than two levels. RETI and RET instructions operate in the same manner except when restoring the contents of the interrupt stack. PD17062...

  • Page 127

    If control is returned to the main routine at this time, BANK and IXE of interrupt A are restored and the main routine operates abnormally. MAIN Undefined Interrupt A RETI MAIN MAIN MAIN Interrupt B RETI RETI PD17062 MAIN Interrupt B RETI MAIN Interrupt C RETI...

  • Page 128

    RETI instruction can be used. However, because the operation of the 17K series emulator differs as shown in Fig. 11-9, the RETI instruction cannot be used for debugging. MAIN MAIN Undefined Interrupt A Interrupt B BANK0 CLR1 IXE RETI PD17062 Interrupt C RETI...

  • Page 129

    Undefined Main routine MAIN If the RETI instruction is used on the emulator, the contents of the bank register and index enable flag of interrupt B are restored. MAIN MAIN Undefined Interrupt A Interrupt B RETI PD17062 Interrupt C RETI...

  • Page 130

    AAA: SUB4: Because the contents of the address stack register (ASR0) are always undefined when the stack pointer is 0, the return addressof the RET instruction also becomes undefined. PD17062 Level 5 Level 6 Level 7 Level 8 Undefined SUB4...

  • Page 131

    POKE INTPM, and interrupt permission registers. Restore the contents of the interrupt PEEK permission register. POKE INTPM, Restores the contents of the window register. PEEK PD17062 pin, and V pin interrupts SYNC pin interrupt using SYNC...

  • Page 132

    V interrupt with a high priority is accepted, the contents SYNC that permits an interrupt is executed in an EI state, are not restored but are saved again in PD17062 pin. interrupt SYNC interrupt processing.

  • Page 133: Timer

    Fig. 12-1 Timer Configuration Control register Timer mode Interrupt Interrupt select permission request (BTM0CK) (INTPM) (INTREQ) Interrupt control block Selector Timer interrupt block Timer carry FF Selector Timer carry FF block PD17062 Timer carry FF judge (BTM0CYJDG) Interrupt request signal...

  • Page 134: Timer Functions

    In the internal timer mode, the timer interval set pulse is generated by dividing the device’s operating frequency (8 MHz). If the frequency deviates from the correct value (8 MHz), the timer interval set pulse will also deviate at the same ratio. PD17062 /TMIN pin.

  • Page 135

    Internal timer 4 ms 1 ms 5 ms 10 Hz /5 (Hz) TMIN Duty cycle PD17062 200 Hz ( 5 ms) Internal timer Internal timer 10 Hz ( 100 ms) Internal timer 50 Hz ( 20 ms) 50 Hz ( 20 ms)

  • Page 136: Timer Carry Flip-flop (timer Carry Ff)

    See Section 12.4 and Chapter 14 for details. Because the BTM0CY flag is a read-only flag, writing to it with the POKE instruction does not affect the operation of the device at all. However, an error is reported by the 17K series assembler. PD17062...

  • Page 137

    Process B Process B' Because it takes long to perform process B' after it is detected that the BTM0CY flag is set at , it is impossible to detect when the BTM0CY flag is set at PD17062 & SKT1 BTM0CY...

  • Page 138

    , it appears to be 1 and causes the timer to , it appears to be 0, and defers the updating of the timer until it is checked CHECK3 PD17062 , and the time interval (100 ms or CHECK3 SKT1 &...

  • Page 139

    As shown above, when the timer carry FF setting time interval is switched, if a newly selected pulse goes low, it allows the BTM0CY flag to preserve its previous state ( the BTM0CY flag to 1 ( in the figure). SET1 BTM0CK0 SKT1 BTM0CY in the figure). If the pulse goes high, it sets PD17062 CLR1 BTM0CK0...

  • Page 140

    If the timer setting time interval is switched right after the BTM0CY flag is checked, the BTM0CY flag remains reset for one cycle, and therefore, the timer error is t PD17062 CHECK CHECK Actual timer interval True timer interval Time interval switched here...

  • Page 141: Cautions In Using The Timer Carry Ff

    (3) A check of the BTM0CY flag takes precedence over a reset sync signal for a CE reset. If both occur at the same time, a CE reset is delayed one cycle. Sections 12.4.1 to 12.4.3 detail the above topics. PD17062...

  • Page 142

    ; Tests the BTM0CY flag. ; Branches to AAA, if 0. BTM0CY flag check Timer update processing time interval CHECK TIMER SKT1 SKT1 BTM0CY BTM0CY CE reset PD17062 If this processing takes long, a CE reset occurs before the processing is completed.

  • Page 143

    ; Because a power failure (power-on reset) is detected, the timer ; carry FF setting time interval is set to 100 ms, and passes ; control to process C. Process C LOOP Fig. 12-6 shows the timing chart for the above program. PD17062...

  • Page 144

    Fig. 12-6 Timing Chart % % % % % % % Timer Timer Timer incremented incremented incre- mented Point B PD17062 # % % Start at Timer Timer address 0 incre- incremented on a CE mented reset Timer updated because...

  • Page 145

    CE reset is deferred by one cycle. Normally, the program starts at address 0000H at this point, but a CE reset does occur because the program to read the BTM0CY flag also happens to run. 500). PD17062...

  • Page 146

    83.33 = n (n is any integer) where t : BTM0CY flag setting time interval : BTM0CY flag read instruction cycle time x number of steps in this program is executed at every 500 instructions, once , a CE reset will not occur forever. PD17062...

  • Page 147: Timer Interrupt

    The timer interrupt request is but the interrupt request is accepted at the same time not accepted because the the IPBTM0 flag is set. IPBTM0 flag is not set. Interrupt enabled pin, V PD17062 Timer interrupt request accepted pin, and serial interface). SYNC...

  • Page 148

    IRQBTM0 flag is set to 1 even in the DI state. In other words, if process A takes 5 ms or longer, an interrupt request will be accepted immediately when a return is made by a RETI instruction, thus disabling process B from being performed. PD17062...

  • Page 149

    In the above case, the time error is: -t SET1 IPBTM0 Interrupt request accepted Interrupt request accepted occurs. to enable interrupts, an interrupt occurs at the negative-going < timer error < 0 PD17062 Interrupt request accepted...

  • Page 150

    , no interrupt occurs because the timer interrupt , the timer interrupt pulse goes low, and the SET1 IRQBTM0 CLR1 IRQBTM0 Interrupt accepted No interrupt accepted , an interrupt request is accepted immediately. PD17062 Timer interrupt pulse switched Interrupt accepted Interrupt accepted , the interrupt request...

  • Page 151: Cautions In Using The Timer Interrupt

    FF is set, a CE reset takes precedence. When the CE reset occurs, it resets the timer interrupt request (IRQBTM0 flag), thus skipping the timer process once. PD17062 at every one second while performing process...

  • Page 152

    FF set pulse, a CE reset does not hamper the normal timer processing, provided that the timer interrupt handling is finished within 10 ms. PD17062...

  • Page 153: Standby

    Fig. 13-1 Standby Block Configuration Interrupt block Timer carry FF /ADC /ADC /ADC /ADC Clock stop block CE pin Halt block Halt control circuit HALT h Clock stop control circuit STOP s Internal clock PD17062 Program counter (PC) Instruction decoder System register Control register...

  • Page 154: Standby Function

    Section 13.3 explains the device operation mode specified at the CE pin. Sections 13.4 and 13.5 describe the halt and clock stop functions. Remark For the PD17062, the operand s of the STOP s instruction must be 0000B. Therefore, the actual instruction is: STOP 0000B...

  • Page 155: Device Operation Mode Specified At The Ce Pin

    Less than 187.5 s STOP instruction disabled (NOP) 187.5 s Less than 187.5 s 187.5 s STOP instruction enabled PD17062 is turned on. CE reset STOP instruction disabled (NOP); a CE reset occurs next time the timer carry FF is set.

  • Page 156: Halt Function

    The CPU is entirely at a stop in the halt state. In the halt state, the program completely stops at the HALT h instruction. In the halt state, however, the peripheral hardware continues operating as it did before execution of the HALT h instruction. PD17062...

  • Page 157

    The halt state is not released even when the condition is satisfied. The halt state is released when the condition is satisfied. Fig. 13-3 Halt Release Conditions pin, timer, V SYNC PD17062 /ADC to P0D /ADC pins). , serial interface) is accepted.

  • Page 158

    Therefore, great care should be taken when an alternate switch is used. The P0D /ADC to P0D /ADC pins are internally pulled down automatically. /ADC Latch /ADC /ADC /ADC General-purpose output port PD17062 /ADC...

  • Page 159

    To solve the above problem, specify the input port so that a low level is input to the A/D converter, before executing the HALT 0001B instruction. to P0D /ADC pins for an A/D converter /ADC /ADC /ADC /ADC General-purpose port pins is selected for an A/D converter (only one pin can be selected PD17062 A/D input Latch...

  • Page 160

    This configuration of the P0D /ADC halt state as shown above. /ADC /ADC /ADC /ADC General-purpose output port to P0D /ADC pins enables a microprocessor to be used to release the PD17062 Latch...

  • Page 161

    ; Specifies the timer carry FF as a halt release condition. ; Built-in macro ; Branches to LOOP2 if the BTM0CY flag is not set. ; Adds 0001B to the contents of M1. ; Built-in macro ; Performs process A if there is a carry. PD17062...

  • Page 162

    After the required interrupt handling is finished, when the RET1 instruction is executed, program control is returned to the instruction just after the HALT instruction. This is explained in the following example. , and serial interface, can be used as a condition to release SYNC PD17062...

  • Page 163

    ; Specifies an interrupt as a halt release condition. pin is issued, the program performs process A. It also pin interrupt, which has a higher hardware priority than the , but this instruction will not be executed. Instead, the timer interrupt PD17062...

  • Page 164: Clock Stop Function

    The clock stop function stops the operation of the 8 MHz crystal oscillator by executing the STOP s instruction. The clock stop function can reduce the current drain of the PD17062 by 10 A (maximum). The operand s of the STOP s instruction is 0000B.

  • Page 165

    FF after the CE pin has been raised to high level. Approx. 50 ms Program starts at address 0 (CE reset) Approx. 50 ms Oscillation stopped Program starts at address 0 (CE reset) PD17062...

  • Page 166

    Process A STOP XTAL The program starts from The STOP XTAL address 0 in synchronization becomes a NOP with setting of the timer carry instruction because FF. (CE reset) the CE pin is high level. PD17062 as shown below, the STOP...

  • Page 167: Operation Of The Device At A Halt Or Clock Stop

    /SCL pins of port 0A are specified as output ports, and the P0A ; Defines a symbol. ; Built-in macro and P0A pins at & , the serial communication continues, and the halt state is PD17062 , specifies a serial interface...

  • Page 168

    Holds the previous state. Operates normally. Operates normally. Operates normally. Stops operating. Operates normally. Operates normally. Operates normally. Stops operating. PD17062 Clock stop Initialized to 0000H and stops. InitializedNote. Holds the previous state. InitializedNote. Stops operating. Stops operating. Stops operating.

  • Page 169

    /HSCNT pin operates as The outputs are preserved. Therefore, if they are pulled down externally during high-level output or pulled up during low-level output, the current drain will increase. PD17062 Clock stop state /SCL and P0A /SDA /SCL and P0A /ADC...

  • Page 170

    RED, GREEN, and BLUE pins output a low level, or the H and V pins are floating. SYNC All pins output a low level. The X pin is internally pulled down, and the X high level. PD17062 SYNC pin outputs a...

  • Page 171: Reset

    Selector BTM0CY flag read Timer carry FF Timer carry disable FF Reset control circuit STOP instruction PD17062 reset), and reset by CE pin (CE Reset signal Forced halt by IRES timer carry FF Control register System register RESET Stack Program counter...

  • Page 172: Reset Function

    Contents controlled by each reset signal Forces the device into the halt state. The halt state is released by the setting of the timer carry FF. Initializes some control registers. Initializes the program counter, stack, system register, and some control registers. PD17062...

  • Page 173: Ce Reset

    CE pin signal rises. It falls in the range from 0 to t (0 < t < t ), which is the selected set time of the timer carry FF . The program continues to run during this period. PD17062...

  • Page 174

    Fig. 14-3 CE Reset Operation When Clock-Stop Used Timer carry FF set pulse IRES RESET Normal operation Clock-stop state Halt state 50 ms STOP Clock stop release CE reset 0000B Oscillation start Program starts from address 0. PD17062...

  • Page 175

    This can be avoided by using a program shown in example 2. ; The last channel is received. ; Main processing ; The changed channel is assigned to general-purpose ; registers R1 and R2. ; The last channel is rewritten. PD17062 . If CE reset is...

  • Page 176

    ; The last channel is received. ; Main processing ; The changed channel is assigned to general-purpose ; registers R1 and R2. ; FLG1 is set while rewriting the last channel. ; The channel is rewritten. . This allows data to be rewritten PD17062...

  • Page 177: Power-on Reset

    (called the power-on clear voltage) or less. rises from 0 V, Power-on clear voltage Device operation stopped Halt state 50 ms Power-on clear release Oscillation start PD17062 exceeds the Power-on reset Program starts from address 0...

  • Page 178

    0000H. drops below 3.5 V, the power-on clear signal is output and operation drops below 2.2 V, the power-on clear signal is output and device rises from 0 V. PD17062 is rising from 0 to 3.5 V.

  • Page 179

    Halt state 50 ms Power-on clear release Power-on reset Oscillation start Program starts from address 0 Power-on clear voltage Device operation stopped Halt state 50 ms Power-on clear release Power-on reset Oscillation start Program starts from address 0 PD17062...

  • Page 180: Relationship Between Ce Reset And Power-on Reset

    14.5.3 When CE Pin Raised after Power-on Reset Fig. 14-6 (c) shows the reset operation. Power-on reset starts the program from address 0000H. CE reset restarts the program from address 0000H at the rising edge of the next timer carry FF set signal. PD17062...

  • Page 181

    Power-on reset Program start Power-on clear voltage Opera- Halt state tion 50 ms Normal operation stopped Power-on reset Program start Power-on clear voltage Opera- Halt state tion stopped Normal operation 50 ms Power-on reset Program start PD17062 CE reset Program start...

  • Page 182

    Raised Opera- tion Halt state stopped Normal operation 50 ms During this period, initialization is per- formed, then the clock is stopped. Power-on reset STOP 0000B Program start PD17062 Power-on clear voltage Back-up...

  • Page 183

    50 ms CE reset STOP Program start 0000B At this point, the power-on clear voltage is switched to 2.2 V. must be raised to Therefore, V below 2.2 V before this point. PD17062 Power-on clear voltage Back-up must not be dropped...

  • Page 184: Power Failure Detection

    Fig. 14-10 shows the BTM0CY flag state transition. Fig. 14-11 shows timing chart and BTM0CY flag operation specified in Fig. 14-10. Program start Power failure detect- Power failure Data memory, output port, etc. initialization PD17062 or by the CE pin, as is turned on, they...

  • Page 185

    CE = L H Normal operation CE reset wait CE = L H Clock oscillation start Forced halt (50 ms) PD17062 CE = high CE reset Rising edge of timer carry FF set pulse CE reset Rising edge of...

  • Page 186

    BTM0CY SKT1 BTM0CY $ ) 1 instruction Fig. 14-12 operation BTM0CY = 0 Power failure Timer time switching STOP Timer time switching BTM0CY = 1 No power failure PD17062 & , STOP 0000B BTM0CY = 1 No power failure...

  • Page 187

    This is also because when the timer carry FF set time is switched before initialization as shown in the example on the next page, initialization by CE reset may not be executed up to the end. PD17062...

  • Page 188

    CE reset CE reset may be applied immediately, depending on the timer carry & FF set time switching timing. When power failure processing may not be executed. PD17062 Power failure detection is too long, a CE reset & is executed before...

  • Page 189: General-purpose Port

    I/O ports in which I/O can be specified in 3-bit (3-pin) units . Fig. 15-1 Block Diagram of General-Purpose Port Column address Data memory Port register BANK0 Out In Example configuration of P0A pins BANK1 BANK2 System register Group I/O Out In Fixed I/O setting PD17062 to pin P0A Control register...

  • Page 190

    Table 15-1 Classification of General-Purpose Ports Classification of general-purpose ports I/O shared port Input-only port Output-only port Target ports Data setting method Bit I/O Port0A Port register Port0B Port1B Group I/O Port1C Port register Port0D Port register Port0C Port register Port1A PD17062...

  • Page 191: Functions Of General-purpose Ports

    Note that reserved words of data memory type are not defined in the port register. Weight of port register bit Port register address (Examples: 70H = A, 71H = B, 72H = C, 73H = D) Port register bank "P" of port PD17062...

  • Page 192

    (1) P0C, P1A P0C and P1A output data is set by P0C (data memory address: 72H of BANK0 or BANK2) and P1A (data memory address: 70H of BANK1) of the port register. See Table 15-2. For details, see Section 15.5. PD17062...

  • Page 193

    Port register (data memory) Bank Address Symbol (bit I/O) (bit I/O) BANK0 BANK2 Output Input Output BANK1 (bit I/O) is read, 0 is always read. PD17062 Bit symbol (reserved word) P0A3 P0A2 P0A1 P0A0 P0B3 P0B2 P0B1 P0B0 P0C3 P0C2 P0C1...

  • Page 194: General-purpose I/o Ports (p0a, P0b, P1b, P1c)

    Sections 15.3.4 and 15.3.5 explain the use of an input port and output port. I/O switching flag Output latch instruction Port register instruction RESET (except P1C) Read instruction (P1C only) I/O switching flag Output Write latch instruction Port register (1 bit) instruction RESET PD17062 Write (1 bit) Read Read...

  • Page 195

    (P1BBIO) Port0B bit I/O selection (P0BBIO) Port0A bit I/O selection (P0ABIO) Power-on Clock stop Flag symbol Flag symbol Flag symbol PD17062 Read/ Address write Sets I/O of each general- purpose port Port0A Port0B Port1B Port1C to P1C pins Input port...

  • Page 196

    Note, however, that the contents of the output latch and the read contents may differ because the two pins, and P0A , are read without changing the pin state. See Section 15.3.6. PD17062...

  • Page 197

    ; Set the P0A , P0A pins as output pins ; Output a high level signal to the P0A ; Output a low level signal to the P0A PD17062 and P0A pins , above, pin with 0.

  • Page 198: General-purpose Input Port (p0d)

    The RESET signal, output upon clock stop, prevents the current drain from increasing due to noise from the input buffer, as explained in Section 15.4.1. P0D is pulled down internally. (4) During halt state The previous state is retained. Write instruction Port register (1 bit) Read instruction Input latch RESET ADC selection signal PD17062...

  • Page 199: General-purpose Output Ports (p0c, P1a)

    (1) and (2), below, show the configuration of the output ports. (1) P0C (P0C , P0C , P0C , P0C pins) (2) P1A (P1A , P1A , P1A , P1A pins) PD17062 Output Write instruction latch Port register (1 bit) Read instruction Output Write instruction latch Port register...

  • Page 200

    The contents of the output latch are output. Since the contents of the output latch are retained, the output data remains as is during the halt state. pins, because of the N-ch open-drain output, are set to the floating PD17062...

  • Page 201: Serial Interface

    16. SERIAL INTERFACE The PD17062 has two sets of serial interface pins, channel 0 (CH0) and channel 1 (CH1), for exchanging data with an external unit. The CH0 pin, which consists of two wires, SDA and SCL, can be operated in any of three modes, clock synchronous two-wire serial input, clock synchronous two-wire serial output, and two-wire bus and SCL pins can be used as general-purpose ports when not being used as a serial interface.

  • Page 202

    Serial I/O-SI, INT-CLK OUT-PORT CK-OUT CLK-OUT+1OUT-PORT SD-OUT CK-OUT Serial I/O-SO, INT-CLK SD-IN CK-IN BUS-SLAVE-RX SD-IN OUT-PORT BUS-MASTER-RX(SOFT-CLK) OUT-PORT IN-PORT 1OUT-PORT+1IN-PORT OUT-PORT OUT-PORT 2OUT-PORT SD-OUT CK-IN BUS-SLAVE-TX SD-OUT OUT-PORT BUS-MASTER-TX(SOFT-CLK) SD-IN CK-OUT BUS-MASTER-RX OUT-PORT CK-OUT CLK-OUT+1OUT-PORT SD-OUT CK-OUT BUS-MASTER-TX PD17062 Operation mode...

  • Page 203

    Serial I/O-SI, INT-CLK, 1IN-PORT SD-IN CK-OUT OUT-PORT Serial I/O-SI, INT-CLK,1OUT-PORT OUT-PORT CK-OUT IN-PORT CLK-OUT,1OUT-PORT, 1IN-PORT OUT-PORT CK-OUT OUT-PORT CLK-OUT, 2OUT-PORT SD-IN CK-OUT SD-OUT Serial I/O-SI/SO, INT-CLK OUT-PORT CK-OUT SD-OUT Serial I/O-SO, INT-CLK, 1OUT-PORT – – – Not to be set PD17062 Operation mode...

  • Page 204

    Since CH1 does not support two-wire bus mode, the SB flag must be set to 0 when CH1 is used. Table 16-5 SIO0CH Channel to be selected Specification of Serial Interface Protocol Protocol Serial I/O mode Two-wire bus mode PD17062...

  • Page 205

    Two-wire bus mode : Slave operation Serial I/O mode : External clock operation Two-wire bus mode : Master operation Serial I/O mode : Internal clock operation Table 16-7 SIO0TX Flag Functions Function is used as a general-purpose port is used as an SO pin PD17062...

  • Page 206: Clock Counter

    Whether the contents of the clock counter became 8 or 9 can be tested in the software by the status register. A request to stop the clock in either transmission mode or reception mode in two-wire bus mode can be handled by the wait register. PD17062 /SCL pin for...

  • Page 207: Status Register

    The SIO0SF9 flag is not influenced by the contents of the serial mode register. This means that the SIO0SF9 flag is set when the contents of the clock counter become 9, even in serial I/O mode. SIO0SF8 SIO0SF9 SBSTT SBBSY PD17062...

  • Page 208

    An operation to read the presettable shift register must be performed while the SIO0SF8 flag is set to 1. The SIO0SF8 flag is not influenced by the contents of the serial mode register. Fig. 16-3 SIO0SF8 and SIO0SF9 Operations SCL, SCK Bit counter SIO0SF8 SIO0SF9 PD17062...

  • Page 209: Wait Register

    16.4 WAIT REGISTER The PD17062 can set a state in which the serial interface hardware does not operate, even if a shift clock is input. This state is called wait mode and is set by the wait register. The wait register consists of four bits; the SIO0WRQ0 flag, which specifies the timing to stop (wait) serial interface communication, SIO0WRQ1 flag, SIO0NWT flag, which indicates if whether the current state is waiting, and the SBACK flag, which indicates whether an acknowledgement is returned in two-wire bus mode.

  • Page 210

    9. high level state when the contents of the clock counter become 9. Waits when the shift clock falls Not to be set with the clock counter set to 8 after detection of the start condition. PD17062 Serial I/O mode...

  • Page 211

    To enable data after waiting, 1 must be written into the SIO0NWT flag as usual. This means that the clock counter is reset to 0 by writing data into the wait register, after which wait is released. PD17062...

  • Page 212

    Normally, wait is instigated at the falling edge of the 8th or 9th bit. Therefore, data should be written into the SBACK flag at this time. Fig. 16-5 Timing of SBACK Rewriting during Wait Clock counter Wait SBACK=1 SBACK=0 SBACK 0 SIO0NWT 1 PD17062...

  • Page 213

    In this case, the contents of the SBACK flag are not influenced by the shift clock. In other words, the SBACK flag is completely isolated from the serial interface. Hence, SBACK can be used as a 1-bit flag for data storage. PD17062...

  • Page 214: Presettable Shift Register (psr)

    The PSR operates as described above not only when using the hardware of the serial interface of the PD17062 (also when using internal or external clock) but also when the clock is generated by the software with the port (P0A ) also used as the shift clock pin set as an output port.

  • Page 215: Serial Interface Interrupt Source Register (sio0imd)

    An interrupt request is generated at the rising edge of the 7th bit of the shift clock immediately after detection of the start condition. An interrupt request is generated upon detection of the stop condition. SIO0IMD3 SIO0IMD2 SIO0IMD1 SIO0IMD0 Function PD17062...

  • Page 216: Shift Clock Frequency Register (sio0ck)

    Fig. 16-7 Configuration of Shift Clock Frequency Register (RF: 39H) Bit position Flag name Table 16-10 Internal Clock Frequencies of Serial Interface SIO0CK1 SIO0CK3 SIO0CK2 SIO0CK1 SIO0CK0 Internal clock frequency 100 kHz 200 kHz 500 kHz 1 MHz PD17062 SIO0CK0...

  • Page 217: D/a Converter

    17.1 PWM PINS The PD17062 has 4 output pins for 6-bit PWM, which enables varying the duty cycle of the 15.625 kHz pulse signal in 64 steps. With this capability, attaching an external lowpass filter to the PD17062 makes it function as a D/A converter.

  • Page 218

    The PWM pin is used as a one-bit output port (through mode), which outputs the content of b Fig. 17-2 Waveform Output from the PWM Pin t = n + 0.75 ( s) (where n is a value specified in the PWMR) 64 s PD17062...

  • Page 219: Pll Frequency Synthesizer

    Fig. 18-1 PLL Frequency Synthesizer Block Diagram Register Data buffer Programmable divider (PD) Note Prescaler PB595 Note External circuit Unlock detection block Phase comparator ( -DET) Reference frequency generator (RFG) Note Voltage-controlled Lowpass filter oscillator (VCO) PD17062 Charge pump Note (LPF)

  • Page 220: Overview Of Each Pll Frequency Synthesizer Block

    Items (1) to (4) briefly describe each block of the synthesizer. (1) Programmable divider (PD) The programmable divider divides the frequency of a signal input from the VCO pin. It uses NEC’s proprietary pulse swallow method to divide a frequency. A division value is given through the data buffer (DBF).

  • Page 221: Programmable Divider (pd) And Pll Mode Select Register

    As shown in Fig. 18-2, the programmable divider consists of a swallow counter and programmable counter. Fig. 18-2 Programmable Divider Configuration Data buffer (DBF) Address Symbol DBF3 DBF2 Data PLL data register 12 bits 1/2 frequency divider Programmable counter PLL disable signal PD17062 DBF1 DBF0 4 bits Swallow counter 4 bits -DET 12 bits...

  • Page 222

    N in the PLL data register (PLLR). Pulse swallow method (where N is 16 bits) See Section 18.7 for how to set the division value (N-value) for each frequency division method. ” of a signal generated in the programmable divider PD17062...

  • Page 223: Reference Frequency Generator (rfg)

    Fig. 18-3 Reference Frequency Generator (RFG) Configuration 8 MHz Divider ” for the PLL frequency synthesizer. is performed using the PLL reference mode select register (at address Control register Address Flag symbol 6.25 kHz Multiplexer 12.5 kHz 25 kHz PD17062 PLL disable signal -DET...

  • Page 224

    Clock stop Flag symbol Address Read/write R/W except PLLRFCK1, which is read-only Specify the reference frequency f frequency synthesizer. 6.25 kHz 12.5 kHz 25 kHz PLL disable Not to be set Fixed at 1 Kept unchanged PD17062 for the PLL...

  • Page 225: Phase Comparator ( -det), Charge Pump, And Unlock Detection Block

    Programmable divider ” of the reference frequency generator, and outputs the up request Address Flag symbol Unlock detection block Delay control Charge pump PLL disable signal PD17062 ” of the programmable divider (PD) Control register Unlock FF P-ch N-ch...

  • Page 226

    The up and down requests are directed to the charge pump and unlock detection block. ”, and outputs the up request signal is lower than the reference frequency f , the phase comparator outputs a down request. , divider output frequency f PD17062 ” of the , the phase comparator outputs , up request...

  • Page 227

    Fig. 18-6 Relationship among f (1) When f is lagging behind f “H” (2) When f is leading f “H” (3) When f is in phase with f “H” “H” (4) When f is lower than f “H” , UP, and DW Signals PD17062...

  • Page 228

    The following paragraphs describe the configuration and functions of the PLL unlock FF judge register and PLL unlock FF delay control register. , and reference : Low level output : High level output : Floating ) of the reference frequency f PD17062...

  • Page 229

    Remark The PLLULJDG is reset when it is read-accessed with a PEEK instruction. ) of the reference frequency f Address Read/write Detects the state of the unlock FF. Unlock FF = 0 : PLL locked Unlock FF = 1 : PLL unlocked Fixed to 0. PD17062 , the content of...

  • Page 230

    Sets the delay time between the reference (f which is necessary to set the unlock FF. 1.25-1.5 s or more 3.5-3.75 s or more 0.25-0.5 s or more Unlock FF disabled (Always to be set) Fixed to 0. Hold PD17062 ) and division frequency (f ) signals,...

  • Page 231: Pll Disable Mode

    Table 18-1 Operation of Each Block During the PLL Disable Mode Block VCO pin Programmable counter Reference frequency generator Phase comparator Charge pump CE pin = low or PLRFMODE = 1111B Pulled down internally Frequency division disabled Output disabled Output disabled Error output pin floating PD17062...

  • Page 232: Setting Data For The Pll Frequency Synthesizer

    13H) are set with data as shown below. 0000 0110 where f : Frequency input to the VCO pin : Reference frequency : Prescaler frequency division ratio = 1743 (decimal) = 06CFH (hexadecimal) PLLR 1100 1111 PD17062 PLRFMODE 0010 6.25 kHz...

  • Page 233: A/d Converter

    19.1 PRINCIPLE OF OPERATION The A/D converter in the PD17062 consists of a 4-bit resistor string-based D/A converter and comparator. The D/A converter is set with data using a 4-bit register (ADCR) mapped at peripheral address 02H. The result of comparison is judged according to the ADCCMP flag in the register file.

  • Page 234: D/a Converter Configuration

    19.2 D/A CONVERTER CONFIGURATION The D/A converter used in the A/D converter of the PD17062 is a resistor string D/A converter consisting of 16 resistors connected in series between the V point is selected. The configuration of the D/A converter is shown in Fig. 19-2.

  • Page 235: Reference Voltage Setting Register (adcr)

    The window register will receive the ADCCMP content as follows: ADCCMP = 0 when input voltage < reference voltage ADCCMP = 1 when input voltage ). It is mapped at bit b0 (LSB) of the register file at address 21H. The reference voltage PD17062...

  • Page 236: Adc Pin Select Register (adcchn)

    If P1C and P0D pins selected as the A/D converter are accessed as ports, “0” is read out. Table 19-2 ADC Pin Selection (LSB) ADCCH1 ADCCH0 Selected pin /ADC /ADC /ADC /ADC /ADC No corresponding pin (do not set) PD17062 (RF : 21H) ADCCMP...

  • Page 237: Example Of A/d Conversion Program

    END: Number of steps in the conversion loop : 17 Conversion time : 34 s (not in DMA mode) Conversion time : 204 s (in DMA mode) PD17062 ; Sets reference voltage. ; Judges comparison result. ; DBF0B3 ; DBF0B2 ;...

  • Page 238

    DBF 1000B Begins AD conversion. ADCR DBF Sets reference voltage. ADCCMP Judges comparison result. DBF0B3 0 DBF0B3 0 DBF0B2 1 DBF0B2 1 Sets reference voltage. ADCR DBF ADCCMP Judges comparison result. DBF0B2 0 DBF0B2 0 DBF0B1 1 DBF0B1 1 PD17062...

  • Page 239

    ADCR DBF Sets reference voltage. ADCCMP Judges comparison result. DBF0B1 0 DBF0B1 0 DBF0B0 1 DBF0B0 1 ADCR DBF Sets reference voltage. ADCCMP Judges comparison result. DBF0B0 0 DBF0B0 0 PD17062...

  • Page 240: Image Display Controller

    Note Up to three control data items can be specified per row. Maximum number of Number of times that display characters per row control data is used per row 14 rows 19 characters Note PD17062 Up to 3 Up to 6 Up to 5 Up to 4 TV screen...

  • Page 241

    Rounding Color specification by R, G, and B Blank (black) Background (TV screen) ROM MAP Characters defined in CROMBANK0 CROMBANK0 cannot be displayed together with 64 fonts those in CROMBANK1 on the same screen. CROMBANK1 56 fonts PD17062 Reverse video...

  • Page 242

    Notes 1. Up to three control data items can be specified per row. 2. Because there is no gap between character positions, kanji and other graphic images can be defined by combining two or more predefined characters. Note 1 15 dots. Note 2 PD17062...

  • Page 243: Direct Memory Access

    In the PD17062, the DMA mode is used to run the IDC. The instruction cycle of the PD17062 is 2 s, but its apparent instruction cycle becomes 12 s during the DMA mode. This does not mean that the actual instruction cycle becomes 12 s, but means that data transfer for the IDC takes 10 s (5 instruction cycles) and execution of an instruction takes one instruction cycle as usual.

  • Page 244

    CLR1 IDCDMAEN Remark The “SET1” or “CLR1” is not included in the PD17062 instruction set. They are a built-in macro instruction of the 17K series assembler. They set or reset a one-bit flag. If they are written in a source program as shown at *1, they are expanded during assembly as shown at *2.

  • Page 245: Idc Enable Flag

    ; If the display is on when VRAM data is to be specified, ; reset the IDCEN (turn off the display). ; Sets VRAM data. ; Makes sure Vsync = low level, and sets the IDCEN. ; Turns on the display. PD17062...

  • Page 246: Vram

    VRAM is the memory that holds data used to select a picture pattern that the IDC displays on a screen such as a TV screen. In the PD17062, the VRAM data is allocated at BANK1 and BANK2 in data memory. One VRAM data item (8 bits) is held at two adjoining addresses (even and odd address).

  • Page 247

    Table 20-3 ID Field Type of data in the data field at 30H). If the data field contains a value of 0 (000000B), B) or 0C0 H (11000000 B). Specifying the BANK of CROM PD17062 to b of the CROM...

  • Page 248

    0B60H-0B6EH 0D70H-0D7EH 0B70H-0B7EH 0D80H-0D8EH 0B80H-0B8EH 0D90H-0D9EH 0B90H-0B9EH 0DA0H-0DAEH 0BA0H-0BAEH 0DB0H-0DBEH 0BB0H-0BBEH 0DC0H-0DCEH 0BC0H-0BCEH 0DD0H-0DDEH 0BD0H-0BDEH 0DE0H-0DEEH 0BE0H-0BEEH 0DF0H-0DFEH 0BF0H-0BFEH PD17062 CROM address BANK0 BANK1 0E00H-0E0EH 0E10H-0E1EH 0E20H-0E2EH 0E30H-0E3EH 0E40H-0E4EH OE50H-0E5EH 0E60H-0E6EH 0E70H-0E7EH 0E80H-0E8EH 0E90H-0E9EH 0EA0H-0EAEH 0EB0H-0EBEH 0EC0H-0ECEH 0ED0H-0EDEH 0EE0H-0EEEH 0EF0H-0EFEH...

  • Page 249

    (2) CROMBNK = 1 Display “VO” appears on the screen. The control data used in this case is “control data 1”. ; Control data 1 ; Control data 2 ; Control data 1 ; Control data 2 at 30H). PD17062...

  • Page 250

    0. If the carriage return data is 010011B, therefore, the VRAM row address is 010B (2H), and the VRAM column address is 0110B (6H); namely, they mean the return data to 26H. Fig. 20-3 Carriage Return Data Configuration ID field Data field VRAM row address Upper 3 bits of the VRAM column address PD17062...

  • Page 251

    Fig. 20-4 Carriage Return Data (8 Bits Including the ID Field) BANK1 BANK1 PD17062...

  • Page 252

    30H) in the register file. Fig. 20-5 Relationship between the Control Data and CROM Address Data in VRAM CROM address FH). to b of the CROM address. Similarly to the pattern select data, Bank data BANK0: 0 BANK1: 1 PD17062...

  • Page 253

    0B6FH 0D7FH 0B7FH 0D8FH 0B8FH 0D9FH 0B9FH 0DAFH 0BAFH 0DBFH 0BBFH 0DCFH 0BCFH 0DDFH 0BDFH 0DEFH 0BEFH 0DFFH 0BFFH PD17062 CROM address BANK1 0E0FH 0E1FH 0E2FH 0E3FH 0E4FH 0E5FH 0E6FH 0E7FH 0E8FH 0E9FH 0EAFH 0EBFH 0ECFH 0EDFH 0EEFH 0EFFH 0F0FH...

  • Page 254

    (d) Always specify carriage return data at the end of a row. (e) Always specify two carriage return data items at the end of a screen. PD17062...

  • Page 255: Character Rom

    Table 20-6 CROM Bank CROM bank CROM address BANK0 0800H-0BFFH BANK1 0C00H-0F7FH 0H to to the right section. The bit that corresponds PD17062 16 bits). An area not ) are 15 steps. The data of 10 EH in CROM form one...

  • Page 256

    0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ROM address Undefined (in the CROM area) "0" (no rimming) PD17062 Pattern data...

  • Page 257

    Fig. 20-8 Example of the Pattern of a Character with Rimming Pattern data ROM address (in the CROM area) Rim data Pattern data Rim data "1" (rimming) PD17062...

  • Page 258

    Table 20-7 Horizontal Size Setting Horizontal size data Standard Double Quadruple Horizontal Vertical position position of control data) Horizontal width Maximum number of display Size of a character characters per row 2.5 s 5.0 s Triple 7.5 s 10.0 s PD17062 Color...

  • Page 259

    If the horizontal size data is a double size, for example, one row has only eight character positions. Table 20-8 Vertical Size Setting Vertical width of a Maximum number of display character (interlace) characters in the vertical direction of the control data) PD17062 corresponding...

  • Page 260

    If the vertical size data is a double size, for example, one screen has only six rows. Column Row 0 Row 1 Row 2 Row 3 Row 4 Row 5 Row 6 Row 7 Row 8 Row 9 Row 10 Row 11 Row 12 Row 13 Fig. 20-10 Display Positions PD17062 corresponding Column...

  • Page 261

    B pin). Table 20-9 lists the correspondence between the color data and the output pins. Table 20-10 summarizes the relationships between the color data setting and output colors. Table 20-9 Color Data Table 20-10 Character Color Color data Character color Black Blue Green Cyan Magenta Yellow White PD17062...

  • Page 262

    Each of these three character types corresponds to one dot and has the following meaning: O : Bright dot : Rimming “ “ : Blank When the expression in the first operand evaluates to 0, the display pattern cannot include #. Operand field Comment field expression, ‘display pattern’ [; comment] PD17062...

  • Page 263: Blank, R, G, And B Pins

    (a) When rimming is not specified Pattern signal (R, G, and B pins) Blank signal (BLANK pin) (b) When rimming is specified Pattern signal (R, G, and B pins) Blank signal (BLANK pin) Fig. 20-11 IDC Output Waveform PD17062...

  • Page 264: Specifying The Display Start Position

    01H. It can be read- and write-accessed using the GET and PUT instructions. Note that the IDC start position setting register should not be written to when the IDCEN flag is 1. Fig. 20-12 IDC Start Position Setting Register Configuration Horizontal start position Vertical start position PD17062...

  • Page 265

    B. (The solid lines indicate the screen when the horizontal position data is 0, and the dotted lines, when the horizontal position data is 1. 4.25 after trailing edge of horizontal synchronizing signal (horizontal start position setting data) Fig. 20-13 Horizontal Shifting PD17062 IDC image area...

  • Page 266

    0, and the dotted lines, when the vertical position setting data is 1. 17 H after the trailing edge of the vertical sync signal (vertical start position setting data) Fig. 20-14 Vertical Shifting PD17062 IDC image area...

  • Page 267

    The vertical start position of the display character is determined by the vertical start position register. At this point, the vertical start position (number of horizontal scan lines) depends on the state of the V signals supplied to the PD17062, as shown in Fig. 20-15. In other words, the first H SYNC after the V signal rises is counted as 1 H.

  • Page 268: Sample Programs

    VRAM8 2.08H VRAM9 2.09H VRAM8 VRAMA 2.0AH VRAMB 2.0BH VRAMC 2.0CH VRAMD 2.0DH VRAME 2.0EH VRAMF 2.0FH Display on the TV screen VRAM1 VRAM2 VRAM3 VRAM4 VRAM9 VRAMA VRAMB VRAMC PD17062 Column CH 02 VRAM5 VRAM6 VRAM7 VRAMD VRAME VRAMF...

  • Page 269

    ; Specifies control code 2. ; Specifies display character data 0. ; Specifies display character data 2. ; CR (carriage return) ; CR (carriage return) ; Make sure Vsync = low level and turns on the display. ; Turns on the display PD17062...

  • Page 270

    ; * * Control data 1 * * ; Horizontal size = standard, and vertical size = standard 0000010110001010B ; Horizontal position = column 11, and vertical position = row 1 ; Color = green (G), and rimming = no PD17062 * * *...

  • Page 271

    O OOO O OOOOO OO O OO OO O O OO O OO O OO OO O OO O O OO OOOO OOO O O OOOO OOO O O ; * * * * * * * 0000000000000000B ; NO USE PD17062...

  • Page 272

    D C P 0, ' D C P 0, ' D C P 0, ' O OO D C P 0, ' OOO O OO O D C P 0, ' O OO O O 0000000000000000B ; NO USE PD17062...

  • Page 273

    D C P 0, ' 0 8 D F 0 0 0 0 PD17062 ; * * * * * * * * ; * * * * * * * * ; * * * * * * * * ;...

  • Page 274: Horizontal Sync Signal Counter

    /HSCNT pin is also used as an I/O port. It is assigned to the must be set as an input port. When is used as an input to the horizontal Peripheral address 04H (R) Gate HSYNC counter Selector RF91Hb (R/W) Gate clock generator PD17062 HSCGT...

  • Page 275: Gate Control Register (hscgt)

    3.375/2 ms (with an error of 0 to 62.5 s). The gate is kept open for 1.69 ms. The input pin is biased. If the input signal is high when the gate is opened or closed, it is counted as one. HSCGT1 HSCGT0 (RF11H) Gate closed Gate open Open-gate time of 1.69 ms Not to be set Fixed at 0 PD17062 Note...

  • Page 276: Hsync Counter (hsc)

    PEEK WR, 0B6H WR, #0111B POKE 0B6H, WR ; Makes sure that the gate is closed once. ; Selects the 1.69 ms gate mode. ; Makes sure that the gate is closed. ; Reads the content of the HSYNC counter. PD17062...

  • Page 277: Instruction Sets

    (page 0) 1 1 0 1 addr (page 1) 1 1 1 0 1 1 1 1 ADDC SUBC SKGE SKLT CALL PD17062 m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 m, r m, #n4...

  • Page 278: Instructions

    : Peripheral address (four low-order bits) : General register column address : Register file address : Register file address (three high-order bits) : Register file address (four low-order bits) : Stack pointer : Stop release condition : Window register : Contents of and m PD17062...

  • Page 279: List Of Instruction Sets

    MPE = 1: (m) (MP, (r)) if MPE = 0: (m) (BANK, m , (r)) SP – 1, ASR PC, PC (PC), PC ASR, SP SP + 1 PD17062 Instruction code Op code Operand 00000 10000 00010 10010 00111 1001...

  • Page 280

    ASR, SP SP + 1 ASR, SP SP + 1 and skip ASR, INTR INTSK, SP SP + 1 INTEF INTEF STOP HALT No operation PD17062 Instruction code Op code Operand 00111 1101 0000 00111 1100 0000 00111 0011 00111...

  • Page 281: Built-in Macro Instructions

    (flag 1) to (flag n) if (flag n) = “0”, then (flag n ) if (flag n) = “1”, then (flag n) if description = NOT flag n, then (flag n ) if description = flag n, then (flag n) (BANK) PD17062...

  • Page 282: Reserved Symbols For Assembler

    23. RESERVED SYMBOLS FOR ASSEMBLER The reserved PD17062 symbols for the assembler are listed below. 23.1 SYSTEM REGISTER Symbol Attribute Value 0.74H 0.75H 0.76H 0.77H 0.78H BANK 0.79H 0.7AH 0.7AH 0.7AH.3 0.7BH 0.7BH 0.7CH 0.7DH 0.7EH 0.7FH 0.7EH.0 0.7FH.3 0.7FH.2 0.7FH.1...

  • Page 283: Port Register

    Bit 0 of port 1A Bit 3 of port 1B Bit 2 of port 1B Bit 1 of port 1B Bit 0 of port 1B Bit 3 of port 1C Bit 2 of port 1C Bit 1 of port 1C PD17062...

  • Page 284: Register Files

    Vsync interrupt edge selection flag INTNC interrupt edge selection flag A/D converter channel selection flag A/D converter channel selection flag A/D converter channel selection flag A/D converter judge flag PLL unlock FF flag Port 1C I/O selection flag PD17062 Description...

  • Page 285

    SIO0 interrupt mode selection flag SIO0 shift clock selection flag (dummy: 0) SIO0 shift clock selection flag (dummy: 0) Serial clock selection Serial clock selection SIO0 interrupt request flag Vsync interrupt request flag Timer 0 interrupt request flag interrupt request flag PD17062...

  • Page 286: Peripheral Hardware Register

    PWM data register 0 PWM data register 1 PWM data register 2 PWM data register 3 Address register PLL data register – CALL/BR/MOVT instruction operand (EPA bit is on) – CALL/BR/MOVT instruction operand (EPA bit is off) Description PD17062 ) setting register...

  • Page 287: Electrical Characteristics

    –40 to +85 (when IDC has stopped) –55 to +125 = –40 to +85 C) Conditions = –20 to +70 C (when CPU, PLL, and IDC are operating) -P1B 4.0 V PD17062 Unit and PWM to PMW Min. Typ. Max.

  • Page 288

    = –10 to +50 C = 5 V 10 %, RH 70 %) Conditions = –20 to +85 C (when CPU, PLL, and IDC are operating) SYNC SYNC SYNC SYNC PD17062 Min. Typ. Max. Unit 4.25 70 %) Min. Typ.

  • Page 289: Package Drawings

    48PIN PLASTIC SHRINK DIP (600 mil) NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) ltem "K" to center of leads when formed parallel. PD17062 ITEM MILLIMETERS INCHES 44.46 MAX.

  • Page 290

    64 PIN PLASTIC QFP ( NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. PD17062 detail of lead end ITEM MILLIMETERS INCHES 17.2±0.2 0.677±0.008 0.551 +0.009 14.0±0.2 –0.008 0.551 +0.009 14.0±0.2...

  • Page 291: Recommended Soldering Conditions

    26. RECOMMENDED SOLDERING CONDITIONS The conditions listed below shall be met when soldering the PD17062. For details of the recommended soldering conditions, refer to our document SMD Surface Mount Technology Manual (IEI-1207) . Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions.

  • Page 292: Appendix Development Tools

    The EMU-17K also enables user to check the contents of the data memory in real time. SE board The SE-17002 is an SE board for the PD17002 and PD17062. It is used solely for (SE-17002) evaluating the system. It is also used for debugging in combination with the in-circuit emulator.

  • Page 293

    Description Name 17K series AS17K is an assembler assembler applicable to the 17K series. (AS17K) In developing PD17062 programs, AS17K is used in combination with a device file (AS17062). Device file AS17062 is a device file for the (AS17062) PD17062 .

  • Page 294

    PD17062 [MEMO]...

  • Page 295

    MOS devices, use conductive trays, magazine cases, shock absorbers, or metal cases that NEC uses for packaging and shipping. Be sure to ground MOS devices during assembling. Do not allow MOS devices to stand on plastic plates or do not touch pins.

  • Page 296

    The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance.

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