NEC PD17062 Datasheet page 60

Mos integrated circuit 4-bit single-chip microcontroller containing pll frequency synthesizer and image display controller
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8.5.3 For MPE = 0 and IXE = 0 (Data Memory Not Modified)
As shown in Table 8-2, data memory addresses are not affected by the index register or data memory row
address pointer.
Example 1. When the row address of the general-purpose register is 0 for BANK0
ADD
03H,
When the above instruction is executed, the contents of general-purpose register 03H and
data memory 11H are added and the result is stored in general-purpose register 03H. (See
Example 1 in Fig. 8-3).
Example 2. When the row address of the general-purpose register is 0 for BANK0
MOV
05H,
MOV
@05H, 34H
When the above instruction is executed, the contents of the data memory at address 34H are
transferred to address 38H. This means that the MOV @ r, m instruction transfers the contents
of data memory m to the same row address (in the above case, 3) as m and the column address
(in the above case, 38H) specified by the contents (in the above case, 8) of general-purpose
register r. (See Example 2 in Fig. 8-3).
Example 3. When the row address of the general-purpose register is 0 for BANK0
MOV
0BH,
MOV
34H
When the above instruction is executed, the contents of the data memory are transferred from
address 3EH to 34H. This means that the MOV m, @r instruction transfers the contents at
the same row address (in the above case, 3) as data memory m and at the column address
(in the above case, 3EH) specified by the contents (in the above case, 0EH) of general-purpose
register r to m (See Example 3 in Fig. 8-3). The (transfer) source and (transfer) destination
are exactly opposite to those in example 2.
60
11H
#8
; 05H
8
; Register indirect transfer
#0EH
; 0BH
0EH
@0BH ; Register indirect transfer
PD17062

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