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10.5.4 HSYNC Counter Data Register
Fig. 10.7 shows how the HSYNC counter data register functions .
The HSYNC counter data register reads the horizontal synchronizing signal count.
When the HSYNC counter data register reaches 3FH, it returns to 00H at the next input.
Name
Symbol
DBF3
Address
0CH
b
b
b
b
b
Bit
15
14
13
12
Data
Don't care
HSYNC counter
100
Fig. 10-7 HSYNC Data Register Functions
Data buffer
DBF2
DBF1
0DH
0EH
b
b
b
b
b
b
11
10
9
8
7
6
5
Don't care
Transfer data
Name
b
b
b
7
6
5
0
0
data register
DBF0
0FH
b
b
b
b
b
4
3
2
1
0
GET
8
Peripheral register
Symbol
b
b
b
b
b
4
3
2
1
0
Valid data
HSC
Horizontal synchronizing signal count
PD17062
Peripheral
Peripheral hardware
address
Horizontal
04H
synchronizing signal
counter
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