Pll Reference Mode Selection Register (13H); Setting Of Intnc Pin Acceptance Pulse Width (15H) - NEC PD17062 Datasheet

9.9 PLL REFERENCE MODE SELECTION REGISTER (13H)

b
3
PLLRFCK3 PLLRFCK2
9.10 SETTING OF INT
NC
b b
3 2
INTNCMD3 INTNCMD2
13H
b b
2 1
PLLRFCK1 PLLRFCK0
PIN ACCEPTANCE PULSE WIDTH (15H)
15H
b b
1 0
INTNCMD1 INTNCMD0
b
0
Reference frequency f
0 0 1 0 6.25 kHz
0 0 1 1 12.5 kHz
0 1 1 0 25 kHz
1 1 1 1 PLL disabled
0 1 1 1
1 0 1 0
Not to be set
1 0 1 1
1 1 1 0
Fixed at 1
Setting of INT pin acceptance pulse width
NC
0 0 0 Edge (no noise canceler)
0 0 1 200 s
0 1 0 400 s
0 1 1 2 ms
1 0 0 4 ms
Fixed at 0
PD17062
setting
r
79