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Table 9-1 Peripheral Hardware Control Functions of Control Registers (1/5)
Control register
Register
Ad-
Read/
dress
write
Stack pointer
01H
R/W
(SP)
Timer 0
09H
R/W
clock select
register
Basic timer 0
carry flip-flop
17H
R
judge register
Interrupt-level
0FH
R
judge register
INT
mode
NC
15H
R/W
select register
Remark *: Retains the previous state.
70
Peripheral hardware control function
b3
b2
Symbol
Function outline
b1
b0
0
Fixed at 0
(SP2)
Stack pointer
(SP1)
(3 bits are valid.)
(SP0)
BTM0ZX
On/off of zerocross circuit
BTM0CK2
Base clock setting of basic
BTM0CK1
timer 0 (internal/external)
BTM0CK0
0
0
Fixed at 0
0
BTM0CY
Detects the carry flip-flop state
Fixed at 0
0
Detects the V
INTVSYN
SYNC
0
Fixed at 0
INTNC
Detects the INT
NC
0
Fixed at 0
INTNCMD2
Selects the pulse width of
INTNCMD1
interrupt accept pulse width
of the INT
pin
NC
INTNCMD0
Set value
0
No operation
Pulse for timer carry flop-flop set
0: 10 Hz (100 ms, internal)
1: 200 Hz (5 ms, internal)
2: 10 Hz (100 ms, internal)
3: 200 Hz (5 ms, internal)
4: f
/5 Hz (external)
TMIN
5: 200 Hz (5 ms, internal)
6: f
/6 Hz (external)
TMIN
7: 200 Hz (5 ms, internal)
Pulse for timer interrupt
0: 200 Hz (5 ms, internal)
1: 10 Hz (100 ms, internal)
2: 50 Hz (20 ms, internal)
3: 50 Hz (20 ms, internal)
4: 200 Hz (5 ms, internal)
5: f
/5 Hz (external)
TMIN
6: 200 Hz (5 ms, internal)
7: f
/6 Hz (external)
TMIN
Reset
pin state
Low level
pin state
Low level
0: Accepts with edge
1: 200 s 2: 400 s 3: 2 ms
4: 4 ms
PD17062
At reset
P
S
C
o
T
E
w
O
e
P
r
O
1
n
7 7
7
Operation
0 0 *
0 1 1
Set
High level
0 0 0
High level
0 0 0
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