NEC PD17062 Datasheet page 12

Pin No.
Symbol
DIP QFP
(GC)
21 20 P1A 4-bit output port. This N-ch open-drain output
3
| | | port has an intermediate withstand voltage.
24 24 P1A
0
26 27 P1B 4-bit I/O port. Each bit can be set for input or
3
| | | output.
29 30 P1B
0
30 31 RED Outputs the character data corresponding to R, G,
31 32 GREEN and B of the IDC display. The output is active-
high.
32 33 BLUE
Outputs the blanking signal for cutting the
33 34 BLANK
video signal of the IDC display. The output is
active-high.
Inputs the horizontal synchronizing signal of the
34 35 H
SYNC
IDC display. The input must be active-low.
Inputs the vertical synchronizing signal of the IDC
35 36 V
SYNC
display. The input must be active-low. The input
signal can generate an interrupt.
Input of port 1C and A/D converter
36 38 P1C /ADC
3 1
• P1C
| | P1C
2
3-bit I/O port
38 45 P1C
1
• ADC
Input of a 4-bit A/D converter
Input of a 4-bit A/D converter
39 46 ADC
0
Serial interface and input for port 0B, port 0A,
40 47 P0B /HSCNT
3
horizontal synchronizing signal counter, and
| | P0B /TMIN
2
timer
43 50 P0B
1
• P0A
P0B /SI
0
4-bit I/O port. Each bit can be set for input or
44 51 P0A /SO
3
output.
| | P0A /SCK
2
• P0B
47 54 P0A /SCL
1
4-bit I/O port. Each bit can be set for input or
P0A /SDA
0
output.
• HSCNT
Inputs the count of the horizontal
synchronizing signal. The input is self-
biased.
• TMIN
Timer input. The pin inputs the commercial
power to be used for the clock.
• SI, SO, SCK
Input/output for the three-wire serial interface
• SI: Serial data input
• SO: Serial data output
• SCK: Shift clock input/output
• SDA, SCL
Input/output for the two-wire serial interface
• SCL: Serial clock input/output
• SDA: Serial data input/output
12
Description
to P1C
3 1
1
to P0A
3 0
to P0B
3 0
Output type At power-on reset
N-ch open-drain Undefined
CMOS push-pull Input
CMOS push-pull Low level
CMOS push-pull Low level
— Input
— Input
CMOS push-pull Input
— Input
N-ch open-drain Input
(P0A , P0A )
1 0
CMOS push-pull
(Other than P0A
1
or P0A )
0
PD17062