Shift Clock Frequency Register (Sio0Ck) - NEC PD17062 Datasheet

16.7 SHIFT CLOCK FREQUENCY REGISTER (SIO0CK)

The shift clock frequency register is a four-bit register for setting the frequency of the internal clock of the
serial interface.
The shift clock frequency register is mapped to address 39H of the register file.
Fig. 16-7 shows the configuration of the shift clock frequency register. The register is not mapped to the
two high-order bits of the shift clock frequency register. If the two high-order bits of the shift clock frequency
register are read, 0 is read from each bit.
Fig. 16-7 Configuration of Shift Clock Frequency Register (RF: 39H)
Table 16-10 Internal Clock Frequencies of Serial Interface
216
Bit position b
3
Flag name SIO0CK3 SIO0CK2
(0)
SIO0CK1 SIO0CK0 Internal clock frequency
0 0
0 1
1 0
1 1
b b b
2 1 0
SIO0CK1 SIO0CK0
(0)
100 kHz
200 kHz
500 kHz
1 MHz
PD17062