Setting Data For The Pll Frequency Synthesizer - NEC PD17062 Datasheet

18.7 SETTING DATA FOR THE PLL FREQUENCY SYNTHESIZER

The following data is necessary to control the PLL frequency synthesizer.
(1) Reference frequency : f
(2) Division value
The following paragraphs explain how to set the PLL data.
(1) Setting reference frequency f
The reference frequency is specified according to the PLL reference mode select register.
(2) Calculating division value N
The division value N is calculated as follows:
f
UCO
N =
P f
r
(3) Example of setting the PLL data
The following example shows how to specify the data required to receive channel 02 of the West Europe
TV system, assuming that the prescaler used here is the PB595 and that the frequency division ratio P
is 8.
Receive frequency
Reference frequency
Intermediate frequency : 38.9 MHz
The division value N is calculated as follows:
f 48250 + 38900
UCO
N = =
P f 8
r
The PLL data register (PLLR, at address 41H) and PLL reference mode select register (PLRFMOD, at address
13H) are set with data as shown below.
0000
0
232
r
: N
r
where f : Frequency input to the VCO pin
UCO
f : Reference frequency
r
P : Prescaler frequency division ratio
: 48.25 MHz
: 6.25 kHz
= 1743 (decimal)
6.25
= 06CFH (hexadecimal)
PLLR
0110 1100
6 C
PLRFMODE
1111 0010
F 6.25 kHz
PD17062