Appendix 6 A List Of Fpga External Terminals - Mitsubishi Electric NZ2GN2S-D41P01 User Manual

Appendix 6
A list of FPGA external terminals is shown below.
Connec- Ter- Exter-
tion cir- minal nal ter-
cuit num- minal
board ber name

System terminal

K25 CLKIN_
SYS

T13 CLKIN_
DDR

G14 RSTL

Microcomputer interface terminal
 A13 PLL_LO
CK

G11 CPU_BU
SCLK

A11 CPU_CS
L0

C12 CPU_CS
L1
 C13 CPU_CS
L2
A List of FPGA External Terminals
Each Func- I/O di-
circuit tions rec-
board tion
func-
tion ter-
minal
name
CLKIN_S Clock Input
YS (crystal
oscillator)
input
CLKIN_D Clock Input
DR (crystal
oscillator)
input (level
shift buffer
output)
RSTL Reset Input
input
PLL_LOC PLL lock Output
K signal
output
CPU_BU Bus clock Input
SCLK input
CPU_CS Chip select Input
L[0] signal
input
CPU_CS Input
L[1]
CPU_CS Input
L[2]
I/O di- I/O I/O Logic
rec- type volt-
tion age
for
each
cir-
cuit
board
 
3.3-V 3.3V
LVCM
OS
 
SSTL- 1.35V
135

3.3-V 3.3V Negative
LVCM
OS
 3.3-V 3.3V Positive
LVCM
OS
 
3.3-V 3.3V
LVCM
OS

3.3-V 3.3V Negative
LVCM
OS

3.3-V 3.3V Negative
LVCM
OS

3.3-V 3.3V Negative
LVCM
OS

Appendix 6 A List of FPGA External Terminals

PU/ Initial state Operating
PD in frequency
Re- After
FPGA
set- reset
ting re-
lease
  
25MHz
  
25MHz
PU L H Asynchronous
PU L L Asynchronous
PU L L 50MHz
PU H H 50MHz
PU H H 50MHz
PU H H 50MHz
APPX
A
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