Ethernet Communication Specifications; Fpga Performance - Mitsubishi Electric NZ2GN2S-D41P01 User Manual

5.3

Ethernet Communication Specifications

This section describes the Ethernet communication specifications of the FPGA module.
Item
Transmission Data transmission speed
specifications
Communication mode
Interface
Maximum frame size
Maximum segment length
Number of cascade
connections
IP version
*1 The data transmission speed can be switched by using the function setting switch 3. ( Page 58 Setting the function setting switches)
*2 For the maximum segment length (length between switching hubs), check with the manufacturer of the switching hub to be used.
5.4

FPGA Performance

This section describes the FPGA performance of the FPGA module.
Item
Operating frequency Input clock
Internal logic operating frequency
External memory operating frequency (DDR3L
SDRAM interface)
Series Manufacturer
Series
Master (frame)
IP, macro (standard circuit part)
Connected device MCU
Memory for logging
Input/output DC input/output
performance
Differential input/output
Analog input/output
Logging
Description
1Gbps or 100Mbps
1000BASE-T Full-duplex
100BASE-TX
RJ45 connector (AUTO MDI/MDI-X)
1518 bytes
*2
100m
1000BASE-T Check with the manufacturer of the switching hub to be used.
100BASE-TX
IPv4
Specifications
25MHz
100MHz
400MHz (maximum value)
Intel
Cyclone V series
5CGXFC7D6F27I7N
PLL
SRAM
DDR3 SDRAM controller (with UniPHY)
R-IN32M4-CL3 manufactured by Renesas
DDR3L SDRAM
Input cycle 100ns (10MHz)
Output cycle 100ns (10MHz)
Latency 130ns
Input cycle 10ns (100MHz)
Output cycle 10ns (100MHz)
Latency 90ns
Input cycle (ADC) 4s (250KHz)
Output cycle (DAC) 6s (166.67KHz)

Latency
Logging cycle 1s (1MHz)
*1
5 SPECIFICATIONS
5.3 Ethernet Communication Specifications
5
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