Fpga Register Details (Digital I/O Control Part) - Mitsubishi Electric NZ2GN2S-D41P01 User Manual

Cc-link ie tsn fpga module

Table of Contents

FPGA register details (digital I/O control part)

Input filter counter upper limit

Input filter counter upper limit (IOB0_DIO485_I)(B0) (iport_iob0_dio485_filcnt_upper)

Input filter counter upper limit (IOB1_DIO485_I)(B1) (iport_iob1_dio485_filcnt_upper)

Input filter counter upper limit (IOB2_DIO485_I)(B2) (iport_iob2_dio485_filcnt_upper)

Input filter counter upper limit (IOE0_DIO485_I)(E0) (iport_ioe0_dio485_filcnt_upper)

Input filter counter upper limit (IOE1_DIO485_I)(E1) (iport_ioe1_dio485_filcnt_upper)

Input filter counter upper limit (IOE2_DIO485_I)(E2) (iport_ioe2_dio485_filcnt_upper)

■Description

Sets the filter counter upper limit value of the differential (RS-485) input digital filter.

(1) Digital input filter (up/down counter) upper limit value

• 001H to FFFH

• 000H: No filter (through output)

The filter time is given by the following formula. Set each register appropriately.

• Filter time = Filter sampling pulse  Input filter counter upper limit

Set the filter time to a value with a margin from the minimum value of the ON/OFF width to be taken in as an input, taking into

consideration the delay time outside the FPGA.

The following is a rough indication for the filter time for this module.

For general-purpose input

For pulse counting

■FPGA initial value

■Firmware initial value

• DC I/O circuit board: FA0H (4000)

• Differential I/O circuit board: 5DCH (1500)

• Analog I/O circuit board: FA0H (4000)

• No circuit board: FA0H (4000)

■Reset cause

■Precautions and restrictions

• When a DC I/O circuit board is connected to B or E, the settings are disabled.

• When an analog I/O circuit board is connected to E, the settings are disabled.

Appendix 4 FPGA register

Rough indication

60% of the minimum ON/OFF width taken as input

1-phase input: 15% of pulse cycle

FPGA register address