Sample Circuit - Mitsubishi Electric NZ2GN2S-D41P01 User Manual

Sample circuit

Sample circuit operation details
Sample circuit user circuit block diagram is shown below. Also, the register connections (1) to (6) are shown below.
■Block Diagram
di_ioe2_x_clk100m_reg[15:0]
di_ioe2_dio485_i_clk100m_reg
di_iob0_x_clk100m_reg[15:0]
di_iob0_dio485_i_clk100m_reg
ai_ioe2_aival_vald_clk100m_reg
ai_ioe2_aival_0_clk100m_reg[15:0]...
ai_ioe2_aival_b_clk100m_reg[15:0]
ai_ioe1_aival_vald_clk100m_reg
ai_ioe1_aival_0_clk100m_reg[15:0]...
ai_ioe1_aival_b_clk100m_reg[15:0]
ai_ioe0_aival_vald_clk100m_reg
ai_ioe0_aival_0_clk100m_reg[15:0]...
ai_ioe0_aival_b_clk100m_reg[15:0]
tg_05us_tmgpulse_clk100m_1shot_reg
re_rs_usr_logmode_sel_1_0_clk100m_
reg
re_rs_usr_micon_syserr_1_0_clk100m_
reg
IOB0_UNIT[3:0]
IOB1_UNIT[3:0]
IOB2_UNIT[3:0]
IOE0_UNIT[4:0]
re_rs_usr_alwreg_00_clk100m_reg[15:0]...
re_rs_usr_alwreg_0F_clk100m_reg[15:0]
re_rs_usr_wreg_000_clk100m_reg[15:0]...
re_rs_usr_wreg_1FF_clk100m_reg[15:0]
cpu_intpl_in[2:0]
clk100m
rst_n
re_rd_mode_ctrl2_0_clk100m_reg
No. Function
classification
 Pulse generator
(uc3_pls_top)
11 FPGA INTERNAL CIRCUIT
238
11.4 User Circuit Block
User circuit part (uc2_top)
Digital control part (uc3_dig_top)
Ò
Pulse output part (uc3_plsout_top)
Ó
Counter control part (uc3_cnt_top)
32-bit ring counter (2-phase
multiple of 4) (for basic
circuit board 0)
(uc4_cnt_32ring_2pha4multi)
(1)
32-bit ring counter (1-phase
multiple of 1) (for basic
circuit board 0)
(uc4_cnt_32ring_1pha1multi)
(2)
Ô
(3)
(4)
(5)
(6)
(7)
(8)
Pulse generator (uc3_pls_top)
Analog output part (uc3_ao_top)
Ö
Each block
Each block
Ò, Ó, Ô, Õ, Ö
All FFs
usr_rst_n
Description
Generates 1s pulses for the logging control part.
It starts count-up when "Internal operation start/stop" is set to Start (1), and implements a ring counter of the upper limit(1).
Count-up starts when a 0.5s pulse is received from the timing generator. One pulse (clk100m) is output at the upper limit(1).
(9)
(11)
(10)
32-bit ring counter (2-phase
(12)
multiple of 4) (for expansion
circuit board 2)
...
(uc4_cnt_32ring_2pha4multi)
32-bit ring counter (1-phase
multiple of 1) (for expansion
circuit board 2)
...
(uc4_cnt_32ring_1pha1multi)
(13)
(14)
Õ
×, Ø
×
Ø
Logging control part
(uc3_log_top)
uc_logdat_clk100m_reg[431:0]
Logging data selector
(uc4_log_datsel)
uc_logen_clk100m_reg
Logging enable selector
(uc4_log_ensel)
uc_logend_clk100m_reg
Logging end trigger selector
(uc4_log_endsel)
uc_loguserpulse_clk100m_reg
User sampling pulse
selector
(uc4_log_pulsesel)
uc_ioe2_andat_clk100m_reg[31:0]
uc_ioe2_andat_en_clk100m_reg
uc_ioe2_ldac_clk100m_reg[1:0]
uc_ioe1_andat_clk100m_reg[31:0]
uc_ioe1_andat_en_clk100m_reg
uc_ioe1_ldac_clk100m_reg[1:0]
uc_ioe0_andat_clk100m_reg[31:0]
uc_ioe0_andat_en_clk100m_reg
uc_ioe0_ldac_clk100m_reg[1:0]
uc_iob0_y_clk100m_reg[15:0]...
uc_ioe2_y_clk100m_reg[15:0],
uc_iob0_dio485_o_clk100m_reg...
uc_ioe2_dio485_o_clk100m_reg
uc_iob0_dio485_en_clk100m_reg...
uc_ioe2_dio485_en_clk100m_reg
Output block (uc3_msc_top)
re_rs_usr_alrreg_00_clk100m_reg[15:0]...
re_rs_usr_alrreg_F0_clk100m_reg[15:0]
re_rs_usr_rreg_000_clk100m_reg[15:0]...
re_rs_usr_rreg_1FF_clk100m_reg[15:0]
cpu_intpl_out[2:0]
uc_sampling_tmgpulse_clk100m_
1shot_reg[5:0]
uc_err_clk100m_reg