Module Specific Circuit (Nz2Gn2S-D41P01) - Mitsubishi Electric NZ2GN2S-D41P01 User Manual

Module specific circuit (NZ2GN2S-D41P01)

Digital input control part (di2_top)
The input signal from the input/output selector is loaded into the digital input control part.
For the DC input circuit board, the 16-bit digital signal is multiplexed into the lower 8 bits and the upper 8 bits on the DC input/
output circuit board, and loaded in units of 8 bits into the digital input control part.
Spring
clamp
terminal
block
X0...XF
DC input
(B0...E2)
circuit
For the differential input/output circuit board, only 8 bits are loaded. To reduce the external noise of the loaded input signal, it
is output to the user circuit block via a digital filter.
Spring
clamp
terminal
X0...X7
Differential
block (B0...E2)
input circuit
*1 [15:8] is fixed to 0.
■Function List
Item
Demultiplexer module
Digital filter
*1 The data sampling pulse can be selected as the filter sampling pulse according to the register setting value.
11 FPGA INTERNAL CIRCUIT
196
11.3 Standard Circuit
Top part (top1)
I/O selector
IOB0_X[7:0]
(is2_top)
...IOE2_X[7:0]
[7:0]
[15:8]
IOB0_XOEL[0]
...IOE2_XOEL[0]
IOB0_XOEL[1]
...IOE2_XOEL[1]
Timing
generator
(tg2_top)
Top part (top1)
I/O selector
IOB0_X[7:0]
(is2_top)
...IOE2_X[7:0]
Timing
generator
(tg2_top)
Operation
■Demultiplexing circuit
Demultiplexes data multiplexed outside the FPGA and generates
DC input output enable (IOB/Ex_XOEL[1:0]) for the tri-state
buffer outside the FPGA.
■Digital filter circuit
The digital filter implements a 12-bit up/down counter, and the
filter time can be changed by setting the register areas below.
• Filter sampling pulse
• Input filter counter upper limit
■Filter time formula
Filter time = Filter sampling pulse
limit
For the outline operation of the digital filter, refer to the following.
Page 197 Digital filter
Digital input control part (di2_top)
Enable
generation
Data sampling pulse
Filter sampling pulse
Digital input control part (di2_top)
Enable
generation
Data sampling pulse
Filter sampling pulse
*1
 Input filter counter upper
Digital input signal (after filtering)
(B0...E2)
di_iob0_x_clk100m_reg[15:0]
D Q
Digital
...di_ioe2_x_clk100m_reg[15:0]
en
filter
D Q
en
Digital input signal (after filtering)
(B0...E2)
di_iob0_x_clk100m_reg[15:0]
D Q
Digital
...di_ioe2_x_clk100m_reg[15:0]
en
filter
D Q
en
0
Remarks
The timing for multiplexing and demultiplexing is set by the data
sampling timing (B0 to E2). Also, for DC input/output, the data
sampling pulse setting needs to be set to 0.1s or more.
The filter sampling pulse is set by the filter sampling pulse (B/E0
to E2).
The input filter counter upper limit is set by the input filter counter
upper limit upper (IOB0_X0 to IOE0_XF). Also, set the filter
sampling pulse to the same setting as the data sampling pulse.
For details on the FPGA register areas, refer to the following.
Page 502 FPGA register
User circuit
(uc2_top)
Register
part
(re2_top)
*1
User circuit
(uc2_top)
Register
part
(re2_top)