Fpga Design Procedures - Mitsubishi Electric NZ2GN2S-D41P01 User Manual

10.2

FPGA Design Procedures

When editing the user circuit block, change the RTL of the synthesis environment ($HOME\RTL\TOP\UC). For input/output
(terminal list, timing) connected to the user circuit block, refer to the following.
Page 218 Connection block list
10
Page 610 List of User Circuit Block Terminals
Page 220 Module common interface
10 FPGA DEVELOPMENT
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10.2 FPGA Design Procedures