Setting Method - Mitsubishi Electric NZ2GN2S-D41P01 User Manual

Setting method

Use the FPGA Module Configuration Tool to set parameters. ( Page 98 FPGA parameters)
Operating procedure
1.
Set whether to enable or disable the logging function in "Logging function enable/disable".
If set to "Disable", all parameters of the logging function will be disabled.
2.
Set the logging operation mode in "Logging operation mode setting".
3.
Set the buffer operation in the storage operation mode in "Buffer operation setting".
This setting is invalid when "Logging operation mode setting" is set to "Trigger operation mode". Buffer operation in "Trigger
operation mode" is fixed to ring buffer operation.
4.
Set the logging start method in "Select logging start control".
5.
Set whether to use the logging cycle timing pulse or have the user circuit input the pulse as the timing pulse for sampling
the logging data in "Select sampling pulses".
When "Select sampling pulses" is set to "User circuit output", the sampling pulse interval from the user circuit
needs to be 1s or more.
If the sampling pulse interval is less than 1s, logging data may not be sampled. In addition, the logging timing
pulse error (error code: 1300H) is stored in Latest error code (RWr0), and Error status flag (RXA) turns on.
After the Logging timing pulse error (error code: 1300H) is output, until this error is cleared, another logging
timing pulse error (error code: 1300H) will not be output even if a sampling pulse of less than 1s is input.
After the error is cleared, if a sampling pulse of less than 1s is input, a next error is output.
6.
When "Logging cycle timing" is set for "Select sampling pulses" to "Logging cycle timing", set the cycle for sampling the
data to be logged.
Logging cycle timing (tim_log_cyc) (FPGA register address: 1000_2200H) stores the value calculated by the following
formula.
• Logging cycle timing (tim_log_cyc) (FPGA register address: 1000_2200H) = (set value - 1)2 + 1
Ex.
When the setting value is 6s
Logging cycle timing (tim_log_cyc) (FPGA register address: 1000_2200H) = (6-1)  2 + 1 = 11
7.
Set the size of the data to be logged to DDR3L SDRAM in "Logging data size setting".
8.
Set the number of times logging data is to be sampled after a trigger in "Set number of sampling after trigger" when the
trigger operation mode is used.
This setting is invalid if "Storage operation mode" is selected for the "Logging operation mode setting".
Set number of sampling after trigger is set in units of records.
The settable range of post-trigger sampling times is the range that satisfies the following conditions.
• Set number of sampling after trigger < number of records in logging data size setting
9.
With the "Logging data time division setting", the logging data selection part mounted in the sample circuit can be set to
time division mode or non-time division mode.
• Since this is a setting for a module in the user circuit, it will not work if the logging control part of the sample
circuit has been eliminated. Also, this parameter will not work if the logging control part of the sample circuit
has been changed so that time division logging data generation is disabled.
• When the "Logging data time division setting" is set to "Time division mode", only binary format can be used
as the file saving format of logging data.
12 FUNCTIONS
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12.7 Logging Function
12