Time Setting - Mitsubishi Electric NZ2GN2S-D41P01 User Manual

Time setting

Set the time of the timestamp added to the logging data.
The FPGA module does not correct time information for daylight saving time. Set the time corrected for
summer time in the FPGA module.
CC-Link IE TSN communication mode
Set the first time information distributed from the master station during data link with the master station.
If there is no data link with the master station at startup, it starts at 00:00:00 on January 1, 1970.
Standalone mode
Time information can be set by remote buffer memory.
• Time information set (remote buffer memory address: 1600H) ( Page 500 Time information set)
When Time information set (remote buffer memory address: 1600H) is used to set the time information (1), the following
remote buffer memory values are set.
• Time information (year) (remote buffer memory address: 1601H) ( Page 500 Time information (year))
• Time information (month, day, hour) (remote buffer memory address: 1602H) ( Page 501 Time information (month, day,
hour))
• Time information (minutes, seconds) (remote buffer memory address: 1603H) ( Page 501 Time information (minute,
second))
The time information added to records is updated by the FPGA based on the set time. The FPGA time information can be
checked with the following FPGA register areas.
• Time information (year) (lgdw_clock_rddata1) (FPGA register address: 1000_9030H)
• Time information (month, day, hour) (lgdw_clock_rddata2) (FPGA register address: 1000_9032H)
• Time information (minutes, seconds) (lgdw_clock_rddata3) (FPGA register address: 1000_9034H)
• Time information (ms) (lgdw_clock_rddata4) (FPGA register address: 1000_9036H)
• Time information (s) (lgdw_clock_rddata5) (FPGA register address: 1000_9038H)
• If a value outside the setting range is set, the time setting error (error code: 1210H) is stored in Latest error
code (RWr0) and Error status flag (RXA) turns on.
• Time information (ms) (lgdw_clock_rddata4) (FPGA register address: 1000_9036H) and time information
(s) (lgdw_clock_rddata5) (FPGA register address: 1000_9038H) is reset to 0 when the time is set.
• If the time setting is not set, the time will start from January 1, 1970, 00:00:00.00.
When time information is changed during logging
The time information in the record is also changed partway through.
• In CC-Link IE TSN communication mode, when the time is set by the FPGA module by linking with the master station
during logging.
• When the time is changed by the master station by 1 second or more in CC-Link IE TSN communication mode.
• When the time is set by the remote buffer memory during logging in standalone mode.
12 FUNCTIONS
332
12.7 Logging Function