Nz2Gn2S-D41D01, Nz2Gn2S-D41Pd02, Nz2Ex2S-D41D01 - Mitsubishi Electric NZ2GN2S-D41P01 User Manual

NZ2GN2S-D41D01, NZ2GN2S-D41PD02, NZ2EX2S-D41D01

Differential input/output circuit board (input)
The user circuit timing chart when using the differential input/output circuit board is shown below. In addition, the setting
values of the digital input control part in this timing chart are shown below.
No. Target register
1 Filter sampling pulse (B0)
2 Data sampling timing (B0)
3 Input filter counter upper limit (IOB0_X0) (B0) to input filter counter upper limit (IOB0_XF) (B0)
■Timing chart example
clk100m
Internal operation start/stop [0]
[Digital input control part]
Data sampling pulse
tg_sampling_tmgpulse_0_clk100m_1shot_reg
IOB0_XOEL0
IOB0_XOEL1
IOB0_X[7:0]
Lower side digital input signal fetch
Upper side digital input signal fetch
After lower side digital input signal fetch
After upper side digital input signal fetch
Lower side filter processing
Upper side filter processing
[User circuit block]
Digital input signal (B0 after filtering)
di_iob0_x_clk100m_reg[7:0]
Digital input signal (B0 after filtering)
di_iob0_x_clk100m_reg[15:8]
No. Description
1 Sets the internal operation start/stop (mode_ctrl2) (FPGA register address: 1000_0002H) to Start (1).
2 The data sampling timing becomes Enable (1) at each cycle set in Data sampling timing (B0), and the digital input control part operates.
3 Differential input [7:0] is input from outside the FPGA.
4 The data sampling timing becomes Enable (1) at each cycle set in Data sampling timing (B0), and the digital input control part operates.
*1 B0 is explained at the circuit board. B1, B2, E0, E1, and E2 have the same structure.
*2 Changing the filter sampling pulse (B0) and data sampling timing (B0) changes the input timing of the digital input signal (B0 after
filtering) (di_iob0_x_clk100m_reg[15:0]). For details, refer to the following.
Page 193 Timing generator (tg2_top)
Page 195 Connection and setting value notification timing
*3 The same structure is used when using the digital input/output control part as an input (dio_iob0 to b2_dio485_i_clk100m_reg, dio_ioe0
to e2_dio485_i_clk100m_reg). When using the digital input/output control part for digital input control, set dio_iob0 to
b2_dio485_en_clk100m_reg to 0b.
11 FPGA INTERNAL CIRCUIT
228
11.4 User Circuit Block
(I)
(I) L
(I) L
H
(External terminal output)
H
(External terminal output)
(External terminal input)
(Internal)
L
(Internal) L
(Internal)
(Internal)
(Internal)
(Internal)
(I)
(I)
0.1μs
Differential input 1 Differential input 2
Differential input 1
Setting
value
4H
9H
2H each
Differential input 3
Differential input 2 Differential input 3
Fixed to 00H
Digital filter processing
Digital input (after filtering)
Fixed to 00H
Remarks
0.10s
0.1s cycle
