Fpga Register Details (Sample Circuit Register) - Mitsubishi Electric NZ2GN2S-D41P01 User Manual

Cc-link ie tsn fpga module
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FPGA register details (sample circuit register)

The following functions are implemented to control the circuit to be implemented in the sample circuit.
• Always write register
• Always read register
• Write data
• Read Data
Write/read data control register
■Address
Name
Write/read data control register (usr_wrdat_ctrl)
■Description
The firmware controls this register and transfers data to the user circuit.
• When 1 is written to write data control (transient area/cyclic area) and read data control (transient area/cyclic area), it is
automatically cleared by hardware.
• When 1 is written to the write data control (transient area), the write data area (remote register address: 1000_B000H to
1000_B2FFH) is reflected in the user circuit.
• When 1 is written to the write data control (cyclic area), the write data area (remote register address: 1000_B300H to
0_B3FFH) is reflected in the user circuit.
• When 1 is written to the read data control (transient area), the data from the user circuit is reflected in the read data area
(remote register address: 1000_B800H to 1000_BAFFH).
• When 1 is written to the read data control (cyclic area), the data from the user circuit is reflected in the read data area
(remote register address: 1000_BB00H to 1000_BBFFH).
b15
b14
b13
0 (fixed)
(1) Write data control (transient area)
• 1: Enable
• 0: Disable
(2) Write data control (cyclic area)
• 1: Enable
• 0: Disable
(3) Read data control (transient area)
• 1: Enable
• 0: Disable
(4) Read data control (cyclic area)
• 1: Enable
• 0: Disable
■FPGA initial value
0
■Firmware initial value
0
■Reset cause
Reset
■Precautions and restrictions
Write data (transient area) (FPGA register address: 1000_B000H to 1000_B2FFH) and write data (cyclic area) (FPGA register
address: 1000_B300H to 1000_B3FFH) can also be read from and written to unused areas.
APPX
564
Appendix 4 FPGA register
b12
b11
b10
b9
(4)
b8
b7
b6
b5
(3)
0 (fixed)
FPGA register address
1000_A000H
b4
b3
b2
b1
(2)
b0
(1)

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