Module Specific Circuit (Nz2Ex2S-D41A01) - Mitsubishi Electric NZ2GN2S-D41P01 User Manual

Module specific circuit (NZ2EX2S-D41A01)

Analog input control part (ai2_top)
When E0 to E2 are analog input/output circuit boards, it controls the ADC (three elements on one circuit board).
Communication with the ADC uses SPI (Serial Peripheral Interface). In addition, the serial clock output and serial data output
signals are common and the chip select signal is used to control ADC0 to ADC2 individually. ADC register write and read are
sequentially controlled to ADC0, ADC1, and ADC2. A/D conversion controls ADC0 to ADC2 in parallel.
TOP
(top1)
ADADC setting data
Register
ADC read address setting
part
(re2_top)
ADC register read value
A/D conversion value enabled, A/D conversion value*2
ADC data setting timing selection
Timing
generator
Data sampling pulse
(tg2_top)
User circuit data sampling pulse
uc_sampling_tmgpulse_clk100m_1shot_reg
User circuit
A/D conversion value enabled, A/D conversion
(uc2_top)
value CH0...B
ai_ioe0_aival_vald_clk100m_reg
ai_ioe0_aival_0...b_clk100m_reg
*1 It becomes an analog input/output circuit board. It is described in IOE0. IOE1 and IOE2 have the same structure.
*2 ai_ioe0_aival_0 to b_clk100m_reg
■Function List
Item Operation
A/D conversion Sets whether to enable or disable A/D conversion for each circuit board.
enable/disable
■ADC setting circuit
ADC setting
After setting the A/D conversion enable/disable setting to Enable(1), set the
ADC (rewrite all ADC register areas).
The following functions can be used depending on the ADC setting.
• ADC range setting: Sets the analog input range.
• ADC offset: Outputs the A/D conversion value with the ADC offset value
added/subtracted.
• ADC oversampling ratio setting: After the data sampling pulse is input,
the results of sampling by multiples of the ADC oversampling ratio setting
are averaged and output as A/D conversion value.
A/D conversion ■A/D conversion cycle
processing The conversion cycle timing pulse can be selected from the user circuit
block or data sampling timing by A/D conversion timing selection.
• A/D conversion value: Outputs to the user circuit block and register part.
The A/D conversion value is output in 2's complement.
• A/D conversion start: After ADC initialization end, A/D conversion is
started by writing 1 to the A/D conversion start register.
Analog input control part
(ai2_top)
Parallel-to-SPI
conversion
ADC data
write
ADC
initialization
data
SPI-to-parallel
conversion
ADC data
read
A/D conversion
0
timing
1
A/D conversion
value enable, A/D
conversion value
*1
I/O
selector
(is2_top)
IOE0_X0
IOE0_X2
IOE0_X1
IOE0_X4
IOE0_XOEL0
IOE0_XOEL1
IOE0_X7
IOE0_X3
IOE0_YCK0
IOE0_YCK1
IOE0_X5
IOE0_Y0
IOE0_Y1
Remarks

The processing indicated on the left is performed at the
rising edge of the A/D conversion enable/disable
setting.
When A/D conversion enable/disable setting (A/D
conversion enable/disable setting (E0 to E2)) is set to
Enable, the A/D conversion enable/disable setting (A/D
conversion start E0 to E2) is set to Start. After that, A/D
conversion processing is performed.
The A/D conversion cycle is set by the data sampling
timing (B0) to data sampling timing (B2) and data
sampling timing (E0) to data sampling timing (E2) of
the timing control part.
11 FPGA INTERNAL CIRCUIT
ADC0
Spring
CH0 voltage input
clamp
CONVST
terminal
SCLK
CH0 current input
/CS block
SDI
CH1 voltage input
CH1 current input
DOUTA
DOUTB
CH2 voltage input
CH2 current input
CH3 voltage input
BUSY
CH3 current input
*1
ADC1
CH4 voltage input
CONVST
SCLK
CH4 current input
/CS
SDI
CH5 voltage input
CH5 current input
DOUTA
DOUTB
CH6 voltage input
CH6 current input
CH7 voltage input
BUSY
CH7 current input
ADC2
CH8 voltage input
CONVST
SCLK
CH8 current input
/CS
SDI
CH9 voltage input
CH9 current input
DOUTA
DOUTB
CHA voltage input
CHA current input
CHB voltage input
BUSY
CHB current input
205
11.3 Standard Circuit
11