Nz2Ex2S-D41A01 - Mitsubishi Electric NZ2GN2S-D41P01 User Manual

NZ2EX2S-D41A01

Analog input/output circuit board (input)
The user circuit block timing chart when using the analog input/output circuit board is shown below. The setting values for the
analog input control part in this timing chart are shown below.
No. Target register
1 Data sampling timing (E0)
2 A/D conversion enable/disable setting
3 A/D conversion timing selection
4 ADC range setting CH0-3 (E0)
5 ADC range setting CH4-7 (E0)
6 ADC range setting CH8-B (E0)
7 ADC oversampling ratio setting (E0)
8 ADC offset value CH0-1 (E0)
9 ADC offset value CH2-3 (E0)
10 ADC offset value CH4-5 (E0)
11 ADC offset value CH6-7 (E0)
12 ADC offset value CH8-9 (E0)
13 ADC offset value CHA-B (E0)
14 A/D conversion value CH0 (E0) to A/D conversion value
CHB (E0)
Setting Remarks
value
18FH 4s cycle
0001H CH0 to CHB of E0: A/D conversion enable
0000H Select data sampling timing
3333H CH0 to CHB of E0: -9.9 to 9.9V range
3333H
3333H
0000H Oversampling setting is not required.
8080H ADC offset value CHm-n (E0)
Lower byte: Offset value of CHm
8080H
Upper byte: Offset value of CHn
8080H
8080H
8080H
8080H

Monitor register areas that store A/D conversion values
11 FPGA INTERNAL CIRCUIT
11.4 User Circuit Block
11
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