Fpga Register Details (Digital Input Control Part) - Mitsubishi Electric NZ2GN2S-D41P01 User Manual

FPGA register details (digital input control part)

The details of the FPGA register of the digital input control part are shown below.
Input filter counter upper limit
■Address
Name
Input filter counter upper limit (IOB0_X0)(B0) (iport_iob0_0_filcnt_upper) to Input filter counter upper limit (IOB0_XF)(B0)
(iport_iob0_f_filcnt_upper)
Input filter counter upper limit (IOB1_X0)(B1) (iport_iob1_0_filcnt_upper) to Input filter counter upper limit (IOB1_XF)(B1)
(iport_iob1_f_filcnt_upper)
Input filter counter upper limit (IOB2_X0)(B2) (iport_iob2_0_filcnt_upper) to Input filter counter upper limit (IOB2_XF)(B2)
(iport_iob2_f_filcnt_upper)
Input filter counter upper limit (IOE0_X0)(E0) (iport_ioe0_0_filcnt_upper) to Input filter counter upper limit (IOE0_XF)(E0)
(iport_ioe0_f_filcnt_upper)
Input filter counter upper limit (IOE1_X0)(E1) (iport_ioe1_0_filcnt_upper) to Input filter counter upper limit (IOE1_XF)(E1)
(iport_ioe1_f_filcnt_upper)
Input filter counter upper limit (IOE2_X0)(E2) (iport_ioe2_0_filcnt_upper) to Input filter counter upper limit (IOE2_XF)(E2)
(iport_ioe2_f_filcnt_upper)
■Description
Sets the filter counter upper limit value of the DC/differential (RS-422) input digital filter.
b15 b14 b13
0 (fixed)
(1) Digital input filter (up/down counter) upper limit value
• 001H to FFFH
• 000H: No filter (through output)
The filter time is given by the following formula. Set each register appropriately.
• Filter time = Filter sampling pulse  Input filter counter upper limit
Set the filter time to a value with a margin from the minimum value of the ON/OFF width to be taken in as an input, taking into
consideration the delay time outside the FPGA.
The following is a rough indication for the filter time for this module.
Application
For general-purpose input
For pulse counting
■FPGA initial value
0FFFH
■Firmware initial value
• DC I/O circuit board: FA0H (4000)
• Differential I/O circuit board: 5DCH (1500)
• Analog I/O circuit board: FA0H (4000)
• No circuit board: FA0H (4000)
■Reset cause
Reset
APPX
528
Appendix 4 FPGA register
b12 b11 b10 b9
(1)
For DC input
For differential (RS-422) input
b8 b7 b6 b5
Rough indication
60% of the minimum ON/OFF width taken as input
• 1-phase input: 10% of pulse cycle
• 2-phase input: 5% of pulse cycle
• 1-phase input: 15% of pulse cycle
• 2-phase input: 12.5% of pulse cycle
FPGA register address
1000_3000H to 1000_301EH
1000_3020H to 1000_303EH
1000_3040H to 1000_305EH
1000_3060H to 1000_307EH
1000_3080H to 1000_309EH
1000_30A0H to 1000_30BEH
b4 b3 b2 b1 b0