Notes And Restrictions - Mitsubishi Electric NZ2GN2S-D41P01 User Manual

Cc-link ie tsn fpga module
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Notes and restrictions

Notes and restrictions for the standard circuit are shown below.
• Set "Data sampling timing" and "Filter sampling pulse" to be the same.
• Stop the logging operation before accessing DDR3L SDRAM from the MCU.
• Enable logging start after performing all necessary settings such as the operation of the timing generator.
• When the DC input/output circuit board and analog input/output circuit board are connected, the setting of "Differential
output HOLD/CLEAR" becomes invalid.
11 FPGA INTERNAL CIRCUIT
216
11.3 Standard Circuit

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